Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits

Achieving analog layout integrity through learning and migration

“…It is required to identify all sub-circuits in order to form different device groups before performing analog placement [15]. Most of the previous works [6,7,19] apply various graph-based methods to identify analog building blocks. The graph-based methods may become inefficient when the number of devices in an analog circuit or the number of analog circuits in the design repository is large.…”

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

“…Further automation of the template generation is possible using circuit recognition and rule extraction. Methods like the one proposed in [33] could be used to extract symmetry and grouping information, but are not considered in this work. However, the designer only needs to set the fields of symmetry information, the hierarchical partitioning and the relative positioning of cell boxes.…”

Beyond GORDIAN and Kraftwerk

“…For identification of the basic module sets, the natural hierarchy of analog circuits is used. It is identified using structure recognition [60][61][62][63] and represented as a hierarchy tree. The creation of the hierarchy tree is guided by the relevant placement constraints, which help to speed up the enumeration significantly ( Figure 1).…”