Comprehensive investigation of gate oxide short in FinFETs

Dibaj, Roya; Al-Khalili, D.; Shams, M.

doi:10.1109/vts.2017.7928960

Cited by 4 publications

(3 citation statements)

References 7 publications

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“…SRAMs can be designed using FinFET devices, which are three-dimensional, multi-gate transistors [1]. During their manufacturing process, small particles and lithography inconsistencies can result in defects in their structure [19], e.g., partial opens, misplaced connections, and damaged fin structure [2][3][4]. These defects may impact a cell's ability to discharge its BLs during a read operation and hence impact the cell's BL swing, which is the voltage difference between a BL pair when the SA is enabled, i.e., BL swing = |BL−BL|.…”

Section: A Causes and Definitionmentioning

confidence: 99%

“…The complex structure of FinFETs provides improved shortchannel behaviors while overcoming the planar CMOS technology's sub-threshold leakage [1]. Nevertheless, the process to manufacture such an intricate structure may also introduce defects in the transistor's features, such as opens in fins [2], pinholes in the oxide [3], and opens in the 3D gate [4]. These defects may affect FinFET SRAMs and cause Hardto-Detect faults [5] such as Random Read Faults (RRFs), i.e., a significantly reduced bit line swing [6].…”

Section: Introductionmentioning

confidence: 99%

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Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs

Medeiros

Fieback

Gebregiorgis

et al. 2021

2021 IEEE European Test Symposium (ETS)

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Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Random Read Faults (RRFs). Detection of RRFs is not trivial, as they may not lead to incorrect outputs. Undetected RRFs become test escapes, which might lead to no-trouble-found devices and early in-field failures. Therefore, the detection of RRFs is of utmost importance. This paper proposes test solutions to detect RRFs and reduce test escapes. To achieve this, we first statistically analyze the failure rate due to RRFs, followed by an experimental study of stress conditions' (SCs) impact on detecting RRFs, such as test algorithms, supply voltage, and temperature. Based on the results, we propose a new Design-For-Testability (DFT) scheme for FinFET SRAMs to detect such faults using SCs that improve the detection rate of RRFs. This scheme introduces a negligible area and test time overhead while significantly enhancing RRF detection. Hence, using the proposed DFT leads to reduced test escapes and, consequently, higher-quality FinFET SRAMs.

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Section: A Causes and Definitionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs

Medeiros

Fieback

Gebregiorgis

et al. 2021

2021 IEEE European Test Symposium (ETS)

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“…During the manufacturing of FinFET devices, they can be affected by manufacturing defects such as opens in fins [1] and oxide pinholes [2]. In FinFET SRAMs, these defects cause Hard-to-Detect faults [3] such as Undefined State Faults (USFs), i.e., the cell's storing nodes are not in V DD or GND [4].…”

Section: Introductionmentioning

confidence: 99%

Improving the Detection of Undefined State Faults in FinFET SRAMs

Medeiros

Fieback

Copetti

et al. 2021

2021 16th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Undefined State Faults (USFs). Detection of USFs is not trivial, as they may not lead to incorrect functionality. Nevertheless, undetected USFs may have a severe impact on the memory's quality: they can cause random read outputs, which might lead to test escapes and no-trouble-found devices later when the device is already in the field, as well as compromise the circuit's quality by reducing the memory cell's Static Noise Margin (SNM). Therefore, the detection of USF is critical. This paper proposes a test solution to improve the detection of USFs in FinFET SRAMs. To achieve this, we first analyze the impact of USFs on the cell's SNM and bitline swing during read operations. Then, we perform an experimental study of stress conditions' (SCs) impact on sensitizing and detecting USFs. Finally, we propose a dedicated Design-For-Testability (DFT) scheme for FinFET SRAMs to detect such faults. This scheme introduces a small area overhead while significantly improving USF detection. Hence, using the proposed DFT leads to fewer test escapes and higher-quality FinFET SRAMs.

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