Comprehensive Solution for Micro Bump Coplanarity Control

Chen, Wei; Chen, J.H.; Hsu, Yu Ming; Wang, Rung-De; Wang, Yucheng; Ho, Bin-En; Wu, Markus; Pan, Ponder; Ku, Harry; Wang, Kirin; Lu, Calvin; Liu, K.C.; Liao, M.-H.

doi:10.1109/ectc.2019.00259

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Latest Reliability Testing Studies On Advanced Package Assem...1

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2024

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“…are mounted on Si-IF at 2–10 µ interconnect pitch constraints (very dense) [ 102 ]. The control of µBump coplanarity is a reliability risk due to increased chip size, non-uniform µBump layout, and higher µBump density [ 103 ]. Figure 6 displays a model of a CoWoS architecture.…”

Section: Latest Reliability Testing Studies On Advanced Package Assem...mentioning

confidence: 99%

Modern Trends in Microelectronics Packaging Reliability Testing

Bender,

Bernstein,

Boning

2024

Micromachines

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In this review, recent trends in microelectronics packaging reliability are summarized. We review the technology from early packaging concepts, including wire bond and BGA, to advanced techniques used in HI schemes such as 3D stacking, interposers, fan-out packaging, and more recently developed silicon interconnect fabric integration. This review includes approaches for both design modification studies and packaged device validation. Methods are explored for compatibility in new complex packaging assemblies. Suggestions are proposed for optimizations of the testing practices to account for the challenges anticipated in upcoming HI packaging schemes.

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Section: Latest Reliability Testing Studies On Advanced Package Assem...mentioning

confidence: 99%