Comprehensive Understanding of PBTI and NBTI reliability of High-k / Metal Gate Stacks with EOT Scaling to sub-1nm

Abstract

We have established the comprehensive understanging of PBTI and NBTI reliability of high-k/metal gate stacks. When discussing PBTI, it exhibits a universal relationship in terms of fast transient carrier traps and stress voltage due to the positive oxygen vacancies formation. Using metal gate for Tinv scaling is promising for those improving drain current without PBTI lifetime degradation. However, in the case of NBTI, interface state degradation becomes more serious with Tinv scaling. Thus, high quality interfacial layer, such as wet oxide interface, is promising for improvement of NBTI lifetime.

Study of a Negative Threshold Voltage Shift in Positive Bias Temperature Instability and a Positive Threshold Voltage Shift the Negative Bias Temperature Instability of Yttrium-Doped HfO2 Gate Dielectrics

“…It has been reported that in order to understand NBTI in high-k dielectrics, not only interface degradation but also pre-existing and stress-induced bulk defects for hole traps should be considered. 20) However, there are a few reports indicating that a positive shift occurs under a negative stress due to electron traps and positive charge generation in high-k gate dielectrics. 21) In this study, we observed a V th shift in the opposite direction not only for PBTI but also for NBTI due to Y incorporation that generates the new defect in HfO 2 .…”

Impact on Performance, Positive Bias Temperature Instability, and Time-Dependent Dielectric Dreakdown of n-Type Field Effect Transistors Incorporating Mg into HfSiON Gate Dielectrics

“…Since PBTI was not followed by interface state degradation, the cause of the PBTI is electron traps in the high-gate dielectrics, the origin of which is thought to be the oxygen vacancy type defects. 9) Positively charged oxygen vacancies easily capture electrons, since neutral vacancies are more stable compared with positively charged vacancies. 12) We estimate that this suppression in PBTI is due to two causes.…”

“…Of these, PBTI and TDDB are very serious problems for high-/ metal pMOSFETs. There are many reports regarding PBTI degradation [7][8][9] and the breakdown mechanism [10][11][12][13][14][15] of highgate dielectrics. However, the mechanism is still open to question.…”

Impact of Activation Annealing Temperature on the Performance, Negative Bias Temperature Instability, and Time-to-Dielectric Breakdown Lifetime of High-k/Metal Gate Stack p-Type Metal–Oxide–Semiconductor Field Effect Transistors

“…With increasing stress time, it can be observed that I cp increased owing to the increase in interface state density. It is thought that NBTI is basically due to the interface state density increase, resulting from hydrogen depassivation, 9,10,13) the same as in the conventional poly-Si/SiO 2 system. [22][23][24] This indicates that the NBTI improvement with higher temperature activation annealing is based on an interface state condition improvement (Fig.…”

“…Among the many reliability items, NBTI and TDDB are very serious issues for high-k/metal p-type MOSFETs (pMOSFETs). There are many reports regarding the NBTI [8][9][10][11][12][13][14] and breakdown mechanisms [15][16][17][18][19][20] of high-k gate dielectrics and the proposed reliability improvement techniques. High-k gate dielectrics reliability is dependent on not only the highk gate dielectrics formation process, but also other process like such as sidewall formation.…”