Comprehensive Writing Margin Analysis and its Application to Stacked one Diode‐One Memory Device for High‐Density Crossbar Resistance Switching Random Access Memory

Abstract

The sneak current through the neighboring cells interrupts reading of a selected cell in high-resistance state in crossbar resistance switching random access memory (RRAM). As the sneak current mainly originates from a parallel resistance component to a selected cell, write operation, which requires suffi ciently high voltage delivered to the selected cell, has been regarded to have little relevance to the sneak current issue. In this work, it is revealed that an additional voltage drop on the wire resistances of selected word and bit lines causes an increase in voltage for the write operation (programming/erasing), whose degree is associated with the selectivity of the RRAM selector, array size, resistance of the selected cell, and wire resistances. The presence of sneak paths gives rise to an additional concern about the disturbance of the unselected cells, especially when the writing voltage of the selected cell was increased by the aforementioned factors. A fl oating voltage scheme is considered for proposing a unifi ed writing margin analysis model with diode selectors, and a feasible design strategy based on the analysis for an experimental RRAM device employing a diode with an extremely high rectifi cation ratio (8.4 × 10 8 ) is provided. Furthermore, application of the model to the universal RRAM devices, irrespective of their switching polarity, selector types, and adopted voltage schemes, is included. Figure 1. a) Floating or V dd scheme in the RRAM crossbar array. b) Parallel resistor circuit comprised of the selected cell ( R cell ) and the sneak current components ( R sneak ). c) Model RRAM device used in the simulation.

Fully Functional Logic‐In‐Memory Operations Based on a Reconfigurable Finite‐State Machine Using a Single Memristor

“…[22] Furthermore, it was proven that three other asymmetric devices are capable of performing the RFSM logic, revealing the universality of the proposed logic concept. The proposed RFSM logic concept has a framework similar to that of the CRS logic: the terminal voltages are used to denote the logic inputs, and the logic output is represented by the resistance state, implying a strict LIM feature.…”

“…The stacked structure is functionally equivalent to a diode stacked over a URS memory, as shown by the schematic figure at the bottom-right inset of Figure 3a. [22,27] The upper electrode of the diode layer is defined as a top electrode (TE), which corresponds to terminal T 1 described in the logic concept, whereas the electrode under the URS layer is a bottom electrode (BE) corresponding to terminal T 2 . [25] The URS memristor (Pt/TiO 2 /Pt) is located below the diode.…”

What Will Come After V‐NAND—Vertical Resistive Switching Memory?

“…[3,9,62] In fact, it seems that a low interconnection wire resistance is already a critical issue in 3D XPoint, as can be identified from the unusually high W wire in the disclosed device structure. As discussed in the previous section, in V-NAND, the WL and BL are placed along the lateral and vertical directions, making the necessary number of critical patterning steps for WL and BL only one per line, no matter how many layers were stacked, which makes V-NAND very cost-competitive.…”

“…[9,[88][89][90][91][92][93][94][95] Among these, the simple rotation of the planar CBA by 90° cannot be considered a feasible solution because it involves almost identical technical difficulties in making the multilayer stacked planar CBA, including the issue of the increasing number of interconnection wires. As this type of integration scheme was suggested very recently, there is insufficient literature available on it at this time, but there have been several related suggestions and demonstrations.…”

“…[1][2][3][4] There are two general pathways for utilizing the reversible resistive switching (RS) functionalities of diverse materials: 1) using them as a high-density memory with the most probable architecture of the crossbar array (CBA), which is aligned with the extension of Moore's law; and 2) using them as a new computing/memory unit, such as in neuromorphic computing or stateful logic applications, which may coincide with the "beyond-Moore" or "more-than-Moore" approach. [9] A highperformance cell selector must have sufficiently high selectivity and must not interfere with the RS operation of the memory cell. It should be noted compared with V-NAND.…”