Computational sprinting on a hardware/software testbed

Abstract

CMOS scaling trends have led to an inflection point where thermal constraints (especially in mobile devices that employ only passive cooling) preclude sustained operation of all transistors on a chipa phenomenon called "dark silicon." Recent research proposed computational sprinting-exceeding sustainable thermal limits for short intervals-to improve responsiveness in light of the bursty computation demands of many media-rich interactive mobile applications. Computational sprinting improves responsiveness by activating reserve cores (parallel sprinting) and/or boosting frequency/voltage (frequency sprinting) to power levels that far exceed the system's sustainable cooling capabilities, relying on thermal capacitance to buffer heat.Prior work analyzed the feasibility of sprinting through modeling and simulation. In this work, we investigate sprinting using a hardware/software testbed. First, we study unabridged sprints, wherein the computation completes before temperature becomes critical, demonstrating a 6.3× responsiveness gain, and a 6% energy efficiency improvement by racing to idle. We then analyze truncated sprints, wherein our software runtime system must intervene to prevent overheating by throttling parallelism and frequency before the computation is complete. To avoid oversubscription penalties (context switching inefficiencies after a truncated parallel sprint), we develop a sprint-aware task-based parallel runtime. We find that maximal-intensity sprinting is not always best, introduce the concept of sprint pacing, and evaluate an adaptive policy for selecting sprint intensity. We report initial results using a phase change heat sink to extend maximum sprint duration. Finally, we demonstrate that a sprint-and-rest operating regime can actually outperform thermally-limited sustained execution.

Figure-of-merit for phase-change materials used in thermal management

“…To implement sprinting, a chip in a mobile or hand-held device would ideally offer peak power exceeding its sustainable thermal design power (TDP, which is also the maximum steady-state dissipation power) by an order of magnitude or more [11,14]. Because it is not realistic for existing mobile chips to work at such high power due to current chip designs and the power delivery constraints of mobile batteries, we designed a silicon thermal test chip (TTC) as a proxy for the smartphone processor with integrated PCM micro-reservoirs as on-chip phase-change heat sinks.…”

“…One example that has attracted a great deal of attention recently suggests the use of PCMs to store excessive heat generated during intense computation from mobile devices (e.g., cellular phones, tablets), which briefly ($1 s) exceeds the maximum steady-state power dissipation by an order of magnitude. Known as computational sprinting [11][12][13][14], this approach aims to improve responsiveness for bursty computational demands in devices restricted by passive cooling.…”

Adaptive sprinting: How to get the most out of Phase Change based passive cooling

“…In their proposed sprinting technique, all of the cores are activated at the highest V/f setting until the cores hit a temperature threshold, after which the execution continues with a single core. Their follow-up work demonstrates the fea sibility of sprinting on a hardware/software testbed [5]. They also introduce the concept of sprint pacing, where the cores sprint at a lower frequency when half of the thermal capacity is consumed.…”

“…When center cores exhaust their PCM capacity and hit a temperature threshold, the side cores still have thermal headroom to continue sprinting. Existing sprinting policies [4] [5], however, assume that the cores use up the PCM capacity equally over time, thus, if there is a thermal violation, they either switch to a single core operation or put all cores to idle state.…”

Dynamic fine-grained scheduling for energy-efficient main-memory queries

“…Turbo mode is a special case of computational sprinting [21]. It boosts frequency and voltage (frequency sprinting) of a few cores, with a frequency potentially beyond the nominal one, depending on the power and thermal budget and the number of idle cores.…”