Computational Study of Effects of Surface Roughness and Impurity Scattering in Si Double-Gate Junctionless Transistors

Ichii, Masato; Ishida, Rammaru; Tsuchiya, Hiroyuki; Kamakura, Yoshinari; Mori, Nobuya; Ogawa, Masahiro

doi:10.1109/ted.2015.2399954

Cited by 25 publications

(12 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In Reference 12, a charge‐based compact model for JL‐DG‐transistors is developed to investigate the DC and the quasi‐static characteristics of the transistor technology. Researchers in Reference 13 studies electron transport in Si JL‐DG‐transistors using multi‐subband Monte Carlo method, which shows that these transistors can decrease the mobility reduction due to surface roughness scattering and enhance the capability of the current driving.…”

Section: Introductionmentioning

confidence: 99%

“…For example, to find the I ‐ V specifications of cylindrical nanowire junctionless MOSFETs, an analytical quantum‐mechanical model is developed in Reference 13 using the Landauer formalism. The work in Reference 13 considers the relevant quantum effects resulting from the cylindrical carried confinement, and it handles equations for the device features. In Reference 17, using an analytical model approach, authors propose the idea of the Gaussian‐like doping inside the channel of JL‐DG‐transistors.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A nonlinear feed‐forward memory‐less model to fast prediction of threshold voltage in junction‐less double‐gate MOSFETs

Annabestani

Nasserian

Hasanzadeh

et al. 2020

Int J Numerical Modelling

View full text Add to dashboard Cite

Decreasing Drain-Induced-Barrier-Lowering (DIBL) is one of the nondesirable short-channel effects, causes the threshold voltage of the transistor to be reduced by increasing the drain voltage. DIBL makes it impossible for engineers to consider V T as a constant, and it is necessary to calculate V T as a function of the drain voltage. Therefore, to consider the DIBL effect in the design of ICs, a large computational burden is imposed on the system, which slows down the simulation process in circuit-level simulators. Accordingly, a Nonlinear Feed-Forward Memory-Less (NFFML) model using the Gram-Schmidt orthogonalization approach is proposed, which calculates the V T of the new generation of MOSFETs, that is, Junctionless Double-Gate MOSFETs (JL-DG-MOSFETs), with high precision and a significant speed-up in the computation of the model. It is shown that the proposed numerical method is 313 times faster than the state-of-the-art analytical model. The normalized MSE is 0.435% on average, showing that the proposed approach can be a fast and accurate candidate for replacing the analytical modeling.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A nonlinear feed‐forward memory‐less model to fast prediction of threshold voltage in junction‐less double‐gate MOSFETs

Annabestani

Nasserian

Hasanzadeh

et al. 2020

Int J Numerical Modelling

View full text Add to dashboard Cite

show abstract

“…One of the possible candidates for sub-10 nm devices is the junctionless transistors (JLTs), in which an ultrathin semiconductor body with a single doping type in the source, channel, and drain has been proposed 2, 12–15 . A JLT can be regarded as a “gated-resistor” with the absence of PN junctions in the source and drain regions.…”

Section: Introductionmentioning

confidence: 99%

“…With the rapid evolution of semiconductor technology down to the sub-10 nm technology node, nanoscale transistors based on new structures and materials have been explored 1 – 11 . One of the possible candidates for sub-10 nm devices is the junctionless transistors (JLTs), in which an ultrathin semiconductor body with a single doping type in the source, channel, and drain has been proposed 2 , 12 – 15 . A JLT can be regarded as a “gated-resistor” with the absence of PN junctions in the source and drain regions.…”

Section: Introductionmentioning

confidence: 99%

Room-temperature field effect transistors with metallic ultrathin TiN-based channel prepared by atomic layer delta doping and deposition

Cheng

Wang

Chang

et al. 2017

Sci Rep

View full text Add to dashboard Cite

Metallic channel transistors have been proposed as the candidate for sub-10 nm technology node. However, the conductivity modulation in metallic channels can only be observed at low temperatures usually below 100 K. In this study, room-temperature field effect and modulation of the channel resistance was achieved in the metallic channel transistors, in which the oxygen-doped TiN ultrathinbody channels were prepared by the atomic layer delta doping and deposition (AL3D) with precise control of the channel thickness and electron concentration. The decrease of channel thickness leads to the reduction in electron concentration and the blue shift of absorption spectrum, which can be explained by the onset of quantum confinement effect. The increase of oxygen incorporation results in the increase of interband gap energy, also giving rise to the decrease in electron concentration and the blue shift of absorption spectrum. Because of the significant decrease in electron concentration, the screening effect was greatly suppressed in the metallic channel. Therefore, the channel modulation by the gate electric field was achieved at room temperature due to the quantum confinement and suppressed screening effect with the thickness down to 4.8 nm and the oxygen content up to 35% in the oxygen-doped TiN ultrathin-body channel.With the rapid evolution of semiconductor technology down to the sub-10 nm technology node, nanoscale transistors based on new structures and materials have been explored [1][2][3][4][5][6][7][8][9][10][11] . One of the possible candidates for sub-10 nm devices is the junctionless transistors (JLTs), in which an ultrathin semiconductor body with a single doping type in the source, channel, and drain has been proposed 2, 12-15 . A JLT can be regarded as a "gated-resistor" with the absence of PN junctions in the source and drain regions. A gate voltage is applied to control the current by the formation of a depletion region in channel. Because of the absence of PN junctions in JLTs, the ultrafast thermal annealing for the dopant activation in source and drain is not needed, which allows one to fabricate the transistors with smaller channel lengths. Moreover, the presence of PN junctions in metal-oxide-semiconductor field effect transistors (MOSFETs) causes the extension of source/drain depletion charges into the channel, giving rise to severe short-channel effects including the drain-induced barrier lowering and degraded subthreshold slope 2 . Hence the severe short-channel effects can be alleviated in JLTs [15][16][17] . In addition, in the OFF state of JLTs, the effective distance between source and drain is longer than the physical gate length due to the extension of the channel depletion into source and drain, which suppresses the short channel effects in JLTs 17,18 . Accordingly, the junctionless structure provides the solution to overcome the difficulties related to aggressive scaling of MOSFETs. Actually, the JLT with a channel length down to 3 nm has been demonstrated 19 . In order to achieve a high ...

show abstract

“…The scaling of gate oxide thickness is limited by direct tunneling which leads to an increase in the gate leakage current and static power consumption [4]. The recent innovation of a junctionless (JL) MOSFET [5][6][7] facilitates the miniaturization of device size with additional advantages over the conventional MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

Sharma

Jain

Pratap

et al. 2016

Solid-State Electronics

View full text Add to dashboard Cite

Computational Study of Effects of Surface Roughness and Impurity Scattering in Si Double-Gate Junctionless Transistors

Cited by 25 publications

References 25 publications

A nonlinear feed‐forward memory‐less model to fast prediction of threshold voltage in junction‐less double‐gate MOSFETs

A nonlinear feed‐forward memory‐less model to fast prediction of threshold voltage in junction‐less double‐gate MOSFETs

Room-temperature field effect transistors with metallic ultrathin TiN-based channel prepared by atomic layer delta doping and deposition

Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

Contact Info

Product

Resources

About