The Multi Gate transistors (MGT) have been used to improve the transistor device performance at the nanometer scales. MGTs alleviate many problems in the planar devices due to tighter control of the gate on the channel. In this paper the change in the Fin Architecture and Gate Length of the MOS device, is correlated with the Subthreshold Slope (SS) and ON/OFF current ratio. The study is done by conducting experiments and three-dimensional simulations.