Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS

Maricau, Elie; Gielen, Georges

doi:10.1109/jetcas.2011.2135470

Cited by 67 publications

(30 citation statements)

References 49 publications

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“…An equivalent transistor SPICE model (see Fig. 1) for aging estimation is presented in [13]. For HCI and NBTI effects, parameter degradation is modeled as V th , mobility and output conductance degradation (ΔV th , ΔI u and ΔI g0 respectively).…”

Section: Reliability Issuesmentioning

confidence: 99%

Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology

Cai

Wang

Naviner

et al. 2015

Microelectronics Reliability

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Section: Reliability Issuesmentioning

confidence: 99%

Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology

Cai

Wang

Naviner

et al. 2015

Microelectronics Reliability

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“…For that reason a VCO is always tunable. In the recent years, with the advent of CMOS technologies approaching the nano-scale, besides the parasitic effects, the process variability due to fabrication and/or lifetime degradation must also be considered, leading to the study of the circuits´ sensitivity [11]- [14].…”

Section: Fig 2 Lc-vco Topologymentioning

confidence: 99%

“…Generally, in nano-CMOS technology, imperfections in analog and digital circuits are commonly referred as process's parameter variability. Parameter variability is a consequence of several physical processes, which occur during fabrication, such as line edge roughness, random dopant fluctuations and oxide thickness variations [1]- [3]. Since process variability has strong influence on circuit reliability as well as in the circuit lifetime, designers usually are tempted to use large design margins, degrading the circuit performance.…”

Section: Introductionmentioning

confidence: 99%

“…Since process variability has strong influence on circuit reliability as well as in the circuit lifetime, designers usually are tempted to use large design margins, degrading the circuit performance. In order to overcome these issues, reliable assess-ments must be done at design time [1]. The need for obtaining variation tolerant physical designs forces the adoption of new design methodologies, where both parasitics and process variability are accounted for.…”

Section: Introductionmentioning

confidence: 99%

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Optimization-Based Design of Nano-CMOS LC-VCOs

Pereira

Fino

Coito

et al. 2012

Technological Innovation for Value Creation

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Abstract. This paper introduces a variability-aware methodology for the design of LC-VCOs in Nano-CMOS technologies. The complexity of the design as well as the necessity for having an environment offering the possibility for exploring design trade-offs has led to the development of design methodologies based multi-objective optimization procedures yielding the generation of Pareto-optimal surfaces. The efficiency of the process is granted by using analytical models for both passive and active devices. Although physics-based analytical expressions have been proposed for the evaluation of the lumped elements, the variability of the process parameters is usually ignored due to the difficulty to formalize it into an optimization performance index. The usually adopted methodology of considering only optimum solutions for the Pareto surface, may lead to pruning quasi-optimal solutions that may prove to be better, should their sensitivity to process parameter variation be accounted for. In this work we propose starting by generating an extended Pareto surface where both optimum and quasi-optimum solutions are considered. Finally information on the sensitivity to process parameter variations, is used for electing the best design solution.

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“…Generally, in nano-CMOS technology, imperfections in analog and digital circuits are commonly referred as process parameter variability. Parameter variability is a consequence of several physical processes which occur during fabrication, such as line edge roughness, random dopant fluctuations and oxide thickness variations [1][2][3][4]. Since parameter variability has strong influence on circuit reliability as well as in the circuit lifetime, designers are usually tempted to use large design margins, degrading the circuit performance.…”

Section: Introductionmentioning

confidence: 99%