Computer-aided test flow in core-based design

Abstract

This papcr copes with the test-pattern gcneration mid hitl cuverage determilintion in the core-based design. 'l'hc basic corc-test strategy that one has to apply In the coreliiiwd design is stated in this work. A Compuier-Aided Test (CAT) flow i s propcsscd resulting in accurate fault coverage of embedded cores. T h e CAT flow is applied tu a few cores rvilhiii tlic Philips Core Test Pilot IC project. core pravidcr. The determination of accurate faull cnvcragc in this environment is also included in thc ihird section. Tho core-based test flow has been applied to a Philips pilot IC and the rcsults are presented in scction IV. Scction V concludes thc paper.Thc developincnt of scmiconductor technology in recent years arid thc strong expectation, that this ircnd will l'urbcrmorc conrinuc, ciiahlc the design of complete sysrcnu-on-chip (SOC). In order to use the design rcsourccs in an efficient manner while building such systcms, a iicw design style, Core-based design, has been estatilislied. The main point of the Core-bascd design style is thc integration of reusable, parametrized blocks, so cdlcd cows. Corcs, also described as IP's (Intelleciunl Properly), modules or Mocks, can appenr in hard iny you^), firm (nctlist) or soft (RTL-lcvcl) form. Core-based design has Icd the IC dosign cc?!nmmity into hvvo groups: cow providcrs and corc users. One of thc challengcs facing design and test engineers in this kind of environment is the elaboration of IL comprehensive tcsl strategy. The itnportance of manufacturing tests for these devices is w r y obvIous if one has their astonishing complcxily in mind.'I'liercforc, special attention has to be paid to design-fortcstnbility (DfT) circuitries and test pattern generation of such complex circuits. An efficient high-coverage test approach is crucial to ensurc that only good products will hc shippcd to lhc customers at rensonnble test costs.'['here have bccn a number of academical and industrial approaclies to tackle this problcm such as the ones described in [ 1-51, etc. In order l o establish the worldwide stnndardisation regarding the core-test, a number of companies discuss IEEE PI500 161. This paper is organised 8s follows. The sccond section outlines briefly the core-based test described within the Philips Core Test Action Group -CTAG [7J. Next, the basic flow of the test-pattcm gencration in an embedded core environment i s explaincd rrum the point of view of the The principal motive for core-based design imd test is the timc-to-market rcduction. Hence, the precomputcd tcris for manufaciuring defects should be linked to the cores. Them arc new challengcs [5] that must be tackled if anc applies core-bascd tmt. First, the description of all tcsi-data aspects of the core such as test protocols, patterns, niodcs, etc. must bt: available. Second, there must be DIT techniques availablc that are suited for thc corc-based design style. Finally, test expansion of core-level tests into IC-lcvcl tests is rcquired. The final goal is high fault coverage constraincd with the lcast nuinb...