Computer architecture and instruction set design

Anagnostopoulos, Paul C.; Michel, M. J.; Sockut, Gary H.; Stabler, George M.; Dam, A. van

doi:10.1145/1499586.1499720

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1975

2020

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Cited by 18 publications

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“…The design cycle time is 2 ~s or 20 machine cycles. Design details are presented in [9]. & Sutherland Sha~ed Picture System," Salt ~ke City, October 1973.…”

Section: C Display Rotatormentioning

confidence: 99%

A fast display-oriented processor

Staudhammer

Eastman

England

1975

Proceedings of the 2nd Annual Symposium on Computer Architecture - ISCA '75

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A detailed study of the basic operations of scan graphics processes led to the design of this generalpurpose exl~ndable processor. Full advantage is taken of evolving trends in ECL technology and large-scale integrated circuits. The design allocates hardwired instructions to critical display functions and provides general-purpose flexibility in externally microprogrammable asynchronous processors.The machine uses instruction set partitioning and is optimized to execute relatively short programs operating on large data bases. The processor is thus not limited to display generation but is rather well suited for other real-time tasks, particularly those operating with autonomous processors which can be added as external devices.

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“…The design cycle time is 2 ~s or 20 machine cycles. Design details are presented in [9]. & Sutherland Sha~ed Picture System," Salt ~ke City, October 1973.…”

Section: C Display Rotatormentioning

confidence: 99%