Computing Architectural Vulnerability Factors for Address-Based Structures

Biswas, Arijit; Racunas, Paul; Cheveresan, Razvan; Emer, Joel; Mukherjee, S.; Rangan, Ram

doi:10.1145/1080695.1070014

Cited by 108 publications

(97 citation statements)

References 11 publications

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“…Our framework uses a Wattch-based power model [18]. In addition, we built the Architecture Vulnerability Factor (AVF) analysis methods proposed in [19,20] to estimate processor microarchitecture vulnerability to transient faults. A microarchitecture structure's AVF refers to the probability that a transient fault in that hardware structure will result in incorrect program results.…”

Section: Experimental Methodologymentioning

confidence: 99%

Informed Microarchitecture Design Space Exploration Using Workload Dynamics

Cho¹,

Zhang²,

Li³

2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

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Section: Experimental Methodologymentioning

confidence: 99%

Informed Microarchitecture Design Space Exploration Using Workload Dynamics

Cho¹,

Zhang²,

Li³

2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

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“…The power consumed by TLB is a significant part of the power consumed by the microprocessor as a whole [1]. Failures in TLB with high probability manifest themselves at the system level [2], [3]. They result in user-visible errors with a probability of over 30% [2].…”

mentioning

confidence: 99%

“…Failures in TLB with high probability manifest themselves at the system level [2], [3]. They result in user-visible errors with a probability of over 30% [2]. Software and algorithmic methods [2], [4] can reduce this probability by only 20-50%, but not eliminate.…”

mentioning

confidence: 99%

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Translation Lookaside buffer on the 65-NM STG dice hardened elements

Stenin¹,

Antonyuk²,

Katunin³

et al. 2018

Telfor J

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“…Soft error resilience has been studied over several decades (dating back to 1978 [97]) with a large body of more recent work at various levels of design hierarchy, such as logic level [21,74], microarchitectural level [43,89], and architectural level [8,49,50,55]. For example, Mukherjee et.…”

Section: Related Workmentioning

confidence: 99%

First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems

Wang¹

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As the semiconductor industry keeps evolving at the pace predicted by Moore's Law, computer system architects are facing increasing challenges from the three major design constraints: performance, power, and reliability. Thermal constraints from a reasonable cooling cost do not scale well as technology evolves. The dwindling scaling on threshold voltage leads to a slower pace of supply voltage scaling. These two effects lead to an increasing power density in current and future technology generations. Reliability has emerged as a primary design constraint due to the smaller feature size and generally lower supply voltage for electronic devices. Transient errors caused by high-energy particle strike and voltage noises are expected to increase significantly in frequency.Performance improvement becomes more challenging for future architectures with limitations set by the power and the resilience constraints.Integration of accelerators to create heterogeneous processors is becoming more common for both power and performance reasons. However, this adds one more dimension to the design space that is already complex due to technology variants, system organizations, application's variability, and so on. Therefore, high-level models are essential for system designers to explore the design space and make decisions in a timely manner. Additionally, the three design constraints compete with each other. For example, resilience-aware techniques, such as DMR and TMR, are expensive in terms of power and performance, low-power designs usually come with a price of lower speed.Consequently, it requires system designers to make trade-offs by considering all the three design constraints at the same time.To address these challenges, we (1) propose an analytical modeling framework called Lumos that is capable of modeling power and performance for heterogeneous architectures with hardware iv v accelerators. Then we (2) use Lumos to explore the design space composed of CPU cores and accelerators, revealing important scaling trend for future heterogeneous architectures. We further (3) propose a rapid modeling framework to characterize resilience across a range of applications in DSP, and image processing domains; And finally we (4) propose an integrated framework to optimize energy-efficiency by trading off design constraints of power, performance and resilience. Acknowledgments

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Computing Architectural Vulnerability Factors for Address-Based Structures

Abstract: Processor designers require estimates of the architectural vulnerability factor (AVF)

Cited by 108 publications

References 11 publications

Informed Microarchitecture Design Space Exploration Using Workload Dynamics

Informed Microarchitecture Design Space Exploration Using Workload Dynamics

Translation Lookaside buffer on the 65-NM STG dice hardened elements

First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems

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