Computing bounds on dynamic power using fast zero-delay logic simulation

Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations

“…When gate delays are characterized as bounds, we determine the transient intervals as well as the minimum and maximum numbers of transitions that signals can make. These algorithms allow us to use very simple zero-delay logic simulation for power analysis as discussed in recent publications [2,3]. Those results are reproduced in Section 4 to demonstrate the usefulness of the present analysis.…”

“…These results are taken from a recent implementation of a power analysis tool [2,3] based on the algorithms discussed in the preceding section. The data consists of power analysis of ISCAS85 benchmark circuits for 1000 random vectors.…”

“…The minimum of the two gives us maxtran = 8. In (b), we consider gate delay bounds (3,5) and find that 8 transitions that must now be at least 3 time units apart can never occur within the output ambiguity interval (6, 23) whose width is only 17 units. From Theorem 2, we get Nd = 6, N = 8 and maxtran = 6.…”