Computing dimension for a reconfigurable photonic tensor processing core based on silicon photonics

Abstract

In the rapidly evolving field of artificial intelligence, integrated photonic computing has emerged as a promising solution to address the growing demand for high-performance computing with ultrafast speed and reduced power consumption. This study presents what we believe is a novel photonic tensor processing core (PTPC) on a chip utilizing wavelength division multiplexing technology to perform parallel multiple vector-matrix multiplications concurrently, allowing for reconfigurable computing dimensions without changing the hardware scale. Specifically, this architecture significantly enhances the number of operations in convolutional neural networks, making it superior to other photonic computing systems. Experimental evaluations demonstrate the high-speed performance of the PTPC, achieving an impressive total computing speed of 0.252 TOPS and a computing speed per unit as high as 0.06 TOPS /unit in a compact hardware scale. Additionally, proof-of-concept application experiments are conducted on benchmark datasets, including the Modified National Institute of Standards and Technology (MNIST), Google Quickdraw, and CIFAR-10, with high accuracies of 97.86%, 93.51%, and 70.22%, respectively, in image recognition and classification tasks. By enabling parallel operations in PTPC on a chip, this study opens new avenues for exploration and innovation at the intersection of silicon photonics, scalable computation, and artificial intelligence, shaping the future landscape of computing technologies.