Computing in Memory With Spin-Transfer Torque Magnetic RAM

Abstract

Abstract-In-memory computing is a promising approach to addressing the processor-memory data transfer bottleneck in computing systems. We propose Spin-Transfer Torque Computein-Memory (STT-CiM), a design for in-memory computing with Spin-Transfer Torque Magnetic RAM (STT-MRAM). The unique properties of spintronic memory allow multiple wordlines within an array to be simultaneously enabled, opening up the possibility of directly sensing functions of the values stored in multiple rows using a single access. We propose modifications to STT-MRAM peripheral circuits that leverage this principle to perform logic, arithmetic and complex vector operations. We address the challenge of reliable in-memory computing under process variations by extending ECC schemes to detect and correct errors that occur during CiM operations. We also address the question of how STT-CiM should be integrated within a generalpurpose computing system. To this end, we propose architectural enhancements to processor instruction sets and on-chip buses that enable STT-CiM to be utilized as a scratchpad memory. Finally, we present data mapping techniques to increase the effectiveness of STT-CiM. We evaluate STT-CiM using a device-to-architecture modeling framework, and integrate cycle-accurate models of STT-CiM with a commercial processor and on-chip bus (Nios II and Avalon from Intel). Our system-level evaluation shows that STT-CiM provides system-level performance improvements of 3.93x on average (upto 10.4x), and concurrently reduces memory system energy by 3.83x on average (upto 12.4x).

Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures

“…Many system-level simulators, such as GEM5 [1], zsim [42], Sniper [43], etc., only cover architectural details for general purpose processor simulation. On the other hand, some existing CiM efforts have attempted to compare different CiM design options by evaluating the energy/performance of the CiM modules or accelerators alone [4,16,24,26,27]. In all cases, the focus is on estimating energy savings due to (i) a lower number of memory accesses in CiM-enabled systems, and (ii) the inherently high internal bandwidth of the memory architecture.…”

“…In general, an instruction that is suitable for CiM is featured with source operands fetched from memory and destination operand stored to memory. One common pattern that prior works [4,24] rely on is a sequence of Load-Load-OP-Store instructions, as shown on the left of Figure 3, in which two load operations obtain the source operands, one "OP" instruction ("add" in the figure) conducts a particular operation, and one store operation saves the result. Then this sequence can be replaced by a CiM instruction, e.g., in-cache operation CiM_add as on the right of Figure 3 [4].…”

“…Recent works (e.g., [4,15,16,17,18,19,20,21,22,23,24,25]) in both CMOS Static Random Access Memory (SRAM) and emerging non-volatile memories (NVMs) have demonstrated various CiM designs at different levels of memory hierarchy. The designs allow computation to occur exactly where data resides, thereby reducing energy and performance overheads associated with data movement.…”

“…Most prior solutions do not provide instruction set architecture (ISA) nor compiler support to automatically determine offloading candidates. Designers have to either manually identify the code snippets for CiM from the entire benchmark (e.g., [19,21,22]), or select specific instruction groups for offloading to the CiM unit for execution (e.g., [4,24]). In the latter two works, memory accesses triggered by a CiM module with custom instructions are identified at compiling time.…”

An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive Applications

“…STT-CiM [10] extends the supported functions from bitwise logic to basic arithmetic and vector operations. At circuit level, the row decoders and SAs are enhanced to enable logic functions.…”