Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration

Abstract

Abstract-Numerous researchers have studied the contention that arises among tasks running in parallel on a multicore processor. Most of those studies seek to derive a tight and sound upper-bound for the worst-case delay with which a processor resource may serve an incoming request, when its access is arbitrated using time-predictable policies such as round-robin or FIFO. We call this value upper-bound delay (ubd). Deriving trustworthy ubd statically is possible when sufficient public information exists on the timing latency incurred on access to the resource of interest. Unfortunately however, that is rarely granted for commercial-of-the-shelf (COTS) processors. Therefore, the users resort to measurement observations on the target processor and thus compute a "measured" ubdm. However, using ubdm to compute worst-case execution time values for programs running on COTS multicore processors requires qualification on the soundness of the result. In this paper, we present a measurement-based methodology to derive a ubdm under round-robin (RoRo) and first-in-first-out (FIFO) arbitration, which accurately approximates ubd from above, without needing latency information from the hardware provider. Experimental results, obtained on multiple processor configurations, demonstrate the robustness of the proposed methodology.

Slow and Steady: Measuring and Tuning Multicore Interference

“…This benchmark suite is of interest for the real-time industry and has been used in the evaluation of other works in this domain, e.g. [12], [11]. We want to see if our approach is statistically better than the original one that did not involve tuning.…”

“…Multicore Timing Anomalies: Shah et al [25] study timing anomalies in multicore processors and show how more aggressive co-existing applications can actually lead to faster execution times. Fernandez et al [11] show how resourcestressing benchmarks may fail to produce safe bounds. Under heavy contention, arbitration policies for shared resources, such as round robin and first-in-first-out, can lead a PUT to suffer a delay that is not as severe as the potential worst case.…”

Modeling Contention Interference in Crossbar-based Systems via Sequence-Aware Pairing (SeAP)

“…Contention analysis approaches exploiting the number of requests of applications (either total [31,36,9,21,28] or pertype [12,10,30]) are accurate for modeling HSR with mutually exclusive access, such as buses. However, building only on access counts does not allow properly modelling the behavior of those devices that support some degree of parallelism, such as the crossbar.…”

Increasing the Reliability of Software Timing Analysis for Cache-Based Processors

“…Increased hardware and software complexity reduces the confidence that can be placed on WCET estimates derived by measurement-based timing analysis (MBTA), the most used timing analysis technique in critical real-time embedded systems [44]. In particular, increased effort is needed on the user to concoct stressing execution scenarios during the (analysistime) test campaign as a means to capture bad scenarios that can arise during system operation [18].…”