Conception of simulating grounded negative inductor and implementation using operational transconductance amplifiers

Kwawsibsam, Adisorn; Lahiri, Abhirup; Jaikla, Winai

doi:10.1109/iscit.2013.6645879

Cited by 2 publications

(2 citation statements)

References 19 publications

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“…8 show that the circuit has a zero point at 620 Hz and a double-pole point at 4.6 MHz, which are determined by R s and C sim , respectively. This is in accordance with the theo- To compare with the similar structures proposed recently [1,3,7,9], Table 2 is compiled, in which the area is calculated by only taking capacitor into account, as it consumes most of the chip area. It is assumed that 1 fF capacitance takes 1 µm 2 of chip area.…”

Section: Simulation Results and Analysissupporting

confidence: 64%

“…There have been a number of attempts to develop inductor simulators, which can perform the analog function of inductance [1][2][3][4][5][6][7][8][9][10][11][12]. The most commonly used structures of these inductor simulators are composed of multiple passive components and complicated operational modules such as current conveyor (CC) [2][3][4][5], current feedback operational amplifier (CFOA) [6], operational trans-conductance amplifier (OTA) [7], current backward trans-conductance amplifier (CBTA) [8] and current differencing buffered amplifier (CDBA) [9]. This is because that they attempt to achieve functional flexibility, i.e., to be reconfigured to form other circuit functions such as frequency dependent negative resistor (FDNR), while aiming at low-frequency applications.…”

Section: Introductionmentioning

confidence: 99%

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An improved CMOS-based inductor simulator with simplified structure for low-frequency applications

Zhong

Lai

et al. 2016

J Comput Electron

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In this paper, an improved inductor simulator structure is presented, which can be configured as either grounded or floating inductor simulator with low component count. To achieve simplified structure, inductor simulator circuits are designed using a minimal number of transistors and small capacitance, rather than the complex components/modules such as current convey and operational trans-conductance amplifier which are traditionally used. The simulation results based on 0.5 µm CMOS process parameters show that the proposed structure is able to produce a broad range of inductance values and compared to other similar structures, it provides wider operational frequency bandwidth for the same or comparable inductance value. Furthermore, the structure can be implemented with much smaller chip area using a small capacitance in the circuit, but at the price that it has a higher minimum operational frequency compared to other structures.

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Section: Simulation Results and Analysissupporting

confidence: 64%