Concurrent detection of control flow errors by hybrid signature monitoring

Chen, Yung-Yuan

doi:10.1109/tc.2005.158

Cited by 13 publications

(22 citation statements)

References 24 publications

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“…In other words, the signature memory space overhead will be relatively low when the length of a DCB is long. The DCB length is shortest in Workload1 test bench programs, so the signature memory space overhead is similarly as those of other existing technologies [29]. …”

Section: Iv2 42 Hardware Overheadmentioning

confidence: 96%

“…The speed and area of the DCT watchdog are 85MHz and 2,512 gates count, respectively. The speed and area of MIPS R-2K and DCT watchdog processor of this paper and those of [29] are listed in Table. 1. The signature memory space overhead is shown in Table. 2.…”

Section: Iv2 42 Hardware Overheadmentioning

confidence: 99%

“…The minimal and maximal fault duration times are a single clock cycle and the total time of simulation, respectively. We will simulate 1,500 times for each P error-rate as that used in [29]. The other parameter of the experiment is the bit number of the F-DCT-S. F-DCT-S will be separated into DC and AC signatures.…”

Section: Iv3 43 Coverage and Latencymentioning

confidence: 99%

“…In summary, suppose a processor provides the fault tolerance instructions like the special instructions used in this paper, the program should try to use the fault tolerance instructions as many as possible to reduce the error detection latency. In order to guarantee the data of simulation in accordance to that used in [29], we were carrying on 1,500 times in the following fault simulation experiment. The single fault was injected into the system for each experiment to get the fault detection latency and coverage.…”

Section: Iv3 43 Coverage and Latencymentioning

confidence: 99%

“…Hardware detection schemes usually use embedded signature monitoring (ESM) technique [1], [3], [18], [19], [23], [25], [26], [27], [29] to detect the errors. In [3], the ESM performance can be measured by:…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

An Efficient Run Time Control Flow Errors Detection by DCT Technique

Lai

Horng

Fan

et al. 2012

2012 International Symposium on Biometrics and Security Technologies

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DCT is usually used in image processing but in this paper we use it to detect the run time control errors. In this paper, using the branch instruction, a program is first divided into several data computing blocks (DCBs); each DCB can then be recognized as an image. To get the signatures of each DCB, we then use one dimension discrete cosine transform (1-D DCT) to compute each DCB to generate the 5-bits relay DCT signature (R-DCT-S) and 32-bits final DCT signature (F-DCT-S). These generated signatures are then embedded into the instruction memory and then used to do the run time error checking. For watchdog, the extra hardware should not reduce the processor performance, not increase the fault detection latency and not increase the memory overhead to store the signatures. As for improving the processor degradation, the whole block error checking is done after the branch instruction; the fault detection latency is improved by checking the intermediate error at the R-type instruction;, and the memory overhead is reduced by storing the R-DCT-S to the unused sections of the R-type instruction. The experimental results show that the proposed watchdog gets very high error detection coverage and shortest error detection latency to detect either single fault or multi-faults. Index Terms-control flow check, embedded signature monitoring technique, data computing block(DCB), error detection coverage, error detection latency, fault injection, watchdog processor

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Section: Iv2 42 Hardware Overheadmentioning

confidence: 96%

Section: Iv2 42 Hardware Overheadmentioning

confidence: 99%

Section: Iv3 43 Coverage and Latencymentioning

confidence: 99%

Section: Iv3 43 Coverage and Latencymentioning

confidence: 99%