Concurrent Error Detection in Montgomery Multiplication over Binary Extension Fields

Hariri, Arash; Reyhani-Masoleh, Arash

doi:10.1109/tc.2010.258

Cited by 25 publications

(40 citation statements)

References 28 publications

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“…The MM was successfully adapted to finite field GFð2 m Þ by Koc and Acar [4]. The MM over GFð2 m Þ is a very efficient solution for the design of a fast architecture and VLSI implementation [5,6]. Hariri and Reyhani-Masoleh have considered concurrent error detection for MM over GFð2 m Þ [6].…”

Section: Introductionmentioning

confidence: 99%

“…The MM over GFð2 m Þ is a very efficient solution for the design of a fast architecture and VLSI implementation [5,6]. Hariri and Reyhani-Masoleh have considered concurrent error detection for MM over GFð2 m Þ [6]. Three different multipliers, namely the bit-serial, digit-serial, and bit-parallel multipliers, have been considered and the concurrent error detection scheme has been derived and implemented for each of them.…”

Section: Introductionmentioning

confidence: 99%

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A semi-systolic Montgomery multiplier over GF(2m)

Kim

Jeon

2015

IEICE Electron. Express

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In this study, we present an efficient finite field arithmetic architecture based on systolic array for multiplication which is a core algorithm for division and exponentiation operations. In order to obtain dedicated area-efficient circuits, we adopt Montgomery multiplication algorithm and systolic array. First of all we induce an efficient arithmetic algorithm from typical Montgomery multiplication using an effective factor, then we design an efficient semi-systolic array based multiplication architecture which is highly suitable for pipelined operations. The proposed multiplier saves at least 40% area complexity as compared to the corresponding existing structures.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A semi-systolic Montgomery multiplier over GF(2m)

Kim

Jeon

2015

IEICE Electron. Express

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“…In [33], the multilinear arithmetic codes are used to protect integer multipliers. In [34]- [39], parity-based codes are used to protect bit-serial, digit-serial and bit-parallel Montgomery modular multiplication over binary fields (MMMobf). In [40] and [41], the authors use nonlinear robust residue codes to protect basic integer multipliers.…”

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confidence: 99%

“…The technique in [33] is applied to protect simple 16-bit and 32-bit integer multipliers. The method in [39] is used to protect MMMobf, and the average error-reporting delay is about 50% of whole MMM computing time. Gaubatz et al [40] and Kulikowski et al [41] mentioned but did not provide any practical implementation of the concept of protecting MMMopf by protecting the internal basic integer multipliers.…”

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confidence: 99%

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Secure Systolic Montgomery Modular Multiplier Over Prime Fields Resilient to Fault-Injection Attacks

Yang

Qin

2015

IEEE Trans. VLSI Syst.

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This paper focuses on the security architecture for Montgomery modular multiplication over prime fields (MMMopfs). We propose a class of noninterleaved systolic secure architectures for MMMopf. Each of the proposed secure architectures has two modules, in which one is a main function module (MFM) which computes MMMopf, the other is an error detection module (EDM) which detects faults either owing to natural causes or deliberate fault injection by an attacker. In our secure architectures, several computing types of systolic array structures are adopted to implement the MFMs, and two errordetecting styles based on linear arithmetic codes are employed to construct the EDMs. We explore various combinations of computing types and error-detecting styles to get some excellent secure architectures. The best implementation of our secure architecture of Style-I can detect 99.9985% of faults in processing elements (PEs), with an average delay of 8.56% of whole Montgomery modular multiplication (MMM) computing time, and about 26.73% overhead resources. Meanwhile, the throughput rate of its MFM is 34.44% higher than that of the best pure MMMopf implementation in literature, with almost the same hardware consumption. The error detection capability, overhead proportion, and the average error-reporting delay of our secure architectures are comparable with or better than Hariri and Reyhani-Masoleh's work on secure MMM over binary extension fields. Moreover, our secure architecture of Style-II can localize 90.63% of injected PEs faults, on condition that the number of affected PEs does not exceed 3. The property of our secure architectures that the injected faults could be localized and detected is novel and valuable.Index Terms-Concurrent error detection, Montgomery modular multiplication (MMM), systolic array.

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