Concurrent Fault Detection in Microprogrammed Control Units

Iyengar,; Kinney,

doi:10.1109/tc.1985.1676637

Cited by 44 publications

(12 citation statements)

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“…The signature monitoring approach [5] is beset with the limitations of non-zero error detection latency, (resulting in error propagation and hence the need for checkpointing to support error recovery), need for the generation of reference signatures along all possible paths, and signature aliasing (leading to fault masking). The method using check symbols [8] considers only microprogrammed controllers and related fault models. Besides, the optimal construction of the check symbols has not been discussed.…”

Section: Inadequacy Of the Previous Methodsmentioning

confidence: 99%

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Monitoring machine based synthesis technique for concurrent error detection in finite state machines

1996

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Abstract. This paper discusses a new design methodology for concurrent error detection in synchronous sequential circuits based on the use of monitoring machines. In this approach, an auxiliary sequential circuit, called the monitoring machine, operates in lock-step with the main machine, such that any fault in either of the two machines is immediately detected. This methodology is independent of the fault model. It can be applied to FSMs with pre-encoded states and can also be used for ones being synthesised. It also provides a systematic framework for the combined optimisation of the main and monitoring machines, and for exploring tradeoffs in their implementation.The design of monitored sequential circuits is a two-fold problem; namely one of designing an optimal monitoring machine given the main machine, and the other of encoding the main machine states so that the resulting monitoring machine is minimal. This paper formally discusses the design of both the main and monitoring machines and techniques for their combined optimisation. Tradeoffs in their implementation based on selective fault detection are also examined.Through experimental results, it is shown that the proposed synthesis technique is eminently suitable for the design of low-cost sequential circuits with concurrent error detection. The monitoring machine is less costly than the main machine. It is also not identical to it. As a result, a monitored sequential circuit has significantly lower hardware cost and improved fault coverage than previous implementations.

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Section: Inadequacy Of the Previous Methodsmentioning

confidence: 99%

“…Iyenger and Kinney [8] address this issue for microprogrammed control units, while [9] and [2] address it for FSMs. It is shown in [8] how check symbols generated by a monitor circuit can be used to check for correct sequencing of microinstructions. In [9], an encoding of the FSM's states using convolutional codes is suggested.…”

Section: Previous Workmentioning

confidence: 99%

Monitoring machine based synthesis technique for concurrent error detection in finite state machines

1996

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“…Several works deal with synthesis of totally self-checking (TSC) Control Units [4,10,16,17], design for testability of controllers [6,7] and self-checking control networks [3,9,14]. Paper [16] presents several schemes for on-line checking of microprogrammed control units, which are based on computing of a set of signatures and inserting of these signatures in a microprogram code at specific locations.…”

Section: Introductionmentioning

confidence: 99%

“…Paper [16] presents several schemes for on-line checking of microprogrammed control units, which are based on computing of a set of signatures and inserting of these signatures in a microprogram code at specific locations. Papers [10] and [17] are also dedicated to the problem of synthesis of self-checking microprogrammed control units. In [10] a design of a special monitor circuit enabling to detect a specified fault set is proposed.…”

Section: Introductionmentioning

confidence: 99%