Concurrent Irrevocability in Best-Effort Hardware Transactional Memory

Titos-Gil, Ruben; Fernández-Pascual, Ricardo; Ros, Alberto; Acacio, Manuel E.

doi:10.1109/tpds.2019.2963030

Cited by 4 publications

(1 citation statement)

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“…Since it is done on hardware transactional memory, it is called as hardware signatures [2]. Hybrid TM implementations are done to eliminate limitations of STM and HTM and to provide a better TM implementation [10], [22], [21]. In case if read and write bits are added to the cache tag to carry on readset and writeset addresses.…”

Section: Introductionmentioning

confidence: 99%

Locality Sensitive Hardware Signature Variants for Hardware Transactional Memory

Sangeetha

Vollala

Ramasubramanian

2021

Preprint

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Lock based techniques have its own limitations like priority inversion, convoying, and deadlock. Lock free techniques overcome those mentioned limitations. Transactional memory (TM) is one leading lock free technique used in recent multi core processors like Intel Haswell and IBM BlueGene/Q. TM has to do data versioning and conflict detection. For conflict detection probabilistic data structure called Bloom Filters are used. Bloom filter based hardware signatures are used in TM. In TM shared memory conflicts like RAW, WAR, and WAW hazards are handled by Bloom Filter (BF). Hardware signatures store memory addresses in hashed form on Bloom filters. Bloom filters are easy to use, performance efficient data structures lead to false positive but never support false negative. Locality sensitive hardware signatures reduce filter occupancy by sharing bits for the contiguous memory addresses, in turn reduces the false positive rate. This paper implements existing H3 – HS and LS – HS proposed by Ricardo Quislant et al. [13]. Also this paper proposes RS – HS, CS – HS, and RO – HS. RO – HS equally spreads addresses among bloom filters thereby reduces filter occupancy. In turn reduced filter occupancy leads to better False Positive Rate.

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Section: Introductionmentioning

confidence: 99%