Conditional termination check min-sum algorithm for efficient LDPC decoders

Abstract

Conditional termination check min-sum algorithm (MSA) using the difference of the first two minima is proposed for faster decoding speed and lower power consumption of low-density parity-check (LDPC) code decoders. Judging from the size of the difference in LDPC decoding scheduling, the proposed method dynamically decides whether the termination checking steps will be skipped or not. The simulation results show that the decoding speed is improved up to 7%, and the power consumption is reduced by up to 16.43% without any loss of error correcting performance. Also, the additional hardware cost of the proposed method is negligible compared to conventional LDPC decoders.

A novel bit flipping decoder for systematic LDPC codes

“…Compared with the conventional SP decoder, MS decoder does not require the SNR estimator, which reduces the decoder implementation size and the power consumption. Thus, implementation of efficient LDPC decoders has been actively studied in various ways such as new decoding algorithm [4], smart scheduling scheme [5] and early termination scheme algorithm [6].…”