Configurable cache subsetting for fast cache tuning

Viana, Pablo; Gordon‐Ross, Ann; Keogh, Eamonn; Barros, Edna; Vahid, Frank

doi:10.1145/1146909.1147085

Cited by 17 publications

(10 citation statements)

References 9 publications

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“…Furthermore, Viana et al [5] demonstrated that configurable cores provide best and near-best configurations. When the design goals are relaxed, Ref.…”

Section: Hardware Specializationmentioning

confidence: 99%

“…When the design goals are relaxed, Ref. [5] demonstrated that the near-best configurations could substitute the best configurations. Using this finding, Alsafrjalani et al [11] designed a configuration subsetting exploration method that determined and grouped best and near-best configurations based on applications' domains.…”

Section: Hardware Specializationmentioning

confidence: 99%

“…Subsequently, we set the number of domains d to three, which corresponds to domains of applications with low, mid-range, and large cache hardware requirements; we use Table 1 as our complete design space, (C = 18); and we set the subset size, s, to four since a four-configuration subset is large enough to represent the complete design space of size 18 [5,11].…”

Section: Selecting Coarse-and Fine-grained Configurationsmentioning

confidence: 99%

“…Furthermore, if the number of configurations evaluated during tuning is narrowed to the most promising best or near-best configuration, then tuning overhead is alleviated. Since applications with similar execution requirements belonged to similar application domains, and have similar, but not necessarily the same, best configurations [5], the design space can be subsetted to a small fraction of the complete design space, while still offering best, or near-best configurations for each application. If these subsets are offered in a multicore system, such as each core is offering a distinct subset, then the multicore system offers adherence to disparate domains of applications, with a small degree of heterogeneity.…”

Section: Introductionmentioning

confidence: 99%

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Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore Systems

Alsafrjalani

Gordon‐Ross

2018

Computers

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Heterogeneous and configurable multicore systems provide hardware specialization to meet disparate application hardware requirements. However, effective multicore system specialization can require a priori knowledge of the applications, application profiling information, and/or dynamic hardware tuning to schedule and execute applications on the most energy efficient cores. Furthermore, even though highly disparate core heterogeneity and/or highly configurable parameters with numerous potential parameter values result in more fine-grained specialization and higher energy savings potential, these large design spaces are challenging to efficiently explore. To address these challenges, we propose a novel configuration-subsetted heterogeneous and configurable multicore system, wherein each core offers a small subset of the design space, and propose a novel scheduling and tuning (SaT) algorithm to efficiently exploit the energy savings potential of this system. Our proposed architecture and algorithm require no a priori application knowledge or profiling, and incur minimal runtime overhead. Results reveal energy savings potential and insights on energy trade-offs in heterogeneous, configurable systems.

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“…Furthermore, Viana et al [5] demonstrated that configurable cores provide best and near-best configurations. When the design goals are relaxed, Ref.…”

Section: Hardware Specializationmentioning

confidence: 99%

Section: Hardware Specializationmentioning

confidence: 99%

Section: Selecting Coarse-and Fine-grained Configurationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore Systems

Alsafrjalani

Gordon‐Ross

2018

Computers

Self Cite

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“…As the beginnings of the system development, in order to decide appropriate architecture, designers explore various hardware architectures by use of simple and coarse abstracted hardware models, and they evaluate their performance, power consumption and chip size issues. It is well-known that parameter tuning methods on architectures, such as buffer memory optimization [1] and tuning cache [2] methods contribute system performance very much. At the later stages of system development, however, the designers may find that the designed system does not satisfy the intended specifications, after its detailed evaluation with practical application software, so that they must start hardware design again from the very beginning.…”

Section: Introductionmentioning

confidence: 99%

Cycle based architecture simulation environment framework (MICS) and its optimization

Miyoshi

Sugino

2008

TENCON 2008 - 2008 IEEE Region 10 Conference

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Cycle based architecture simulation environment framework 'MICS' is proposed. The framework proposes the abstracted interfaces for system components, so that a new simulation environment for a system can be built only by implementing additional components required in its architecture under Mics interface definition. Mics interface also allows to use existing simulation tools as system components. By use of this Mics environment, system designers may try various architectures even at the early phase of system development. And optimization methods for high-speed simulation are described. For an example system design issue, simulation environment for several architectures are built, and their simulating speed and overhead are evaluated.

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Switchable cache: utilising dark silicon for application specific cache optimisations

Nawinne¹,

Javaid

Ragel³

et al. 2016

IET Computers & Digital Techniques

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Caches are used to improve memory access time and energy consumption. The cache configuration which enables the best performance often differs between applications due to diverse memory access patterns. The authors present a new concept, called switchable cache, where multiple cache configurations exist on chip, leveraging the abundant transistors available due to what is known as the dark silicon phenomenon. Only one cache configuration is active at any given time based on the application under execution, while all other configurations remain inactive (dark). They describe an architecture to enable seamless integration of multiple cache configurations, and a novel design space exploration methodology to rapidly predetermine the optimal set of configurations at design-time, for a given group of applications. For design spaces containing trillions of design points, the authors' exploration methodology always found the optimal solution in less than 2 s. The switchable cache improved memory access time by up to 26.2% when compared to a fixed cache.

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Configurable cache subsetting for fast cache tuning

Cited by 17 publications

References 9 publications

Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore Systems

Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore Systems

Cycle based architecture simulation environment framework (MICS) and its optimization

Switchable cache: utilising dark silicon for application specific cache optimisations

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