Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Zhang, Jian; Tang, Xianglu; Gaillardon, Pierre-Emmanuel; Micheli, Giovanni De

doi:10.1109/tcsi.2014.2333675

Cited by 79 publications

(28 citation statements)

References 27 publications

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“…Considering the reconfiguration procedure, the NAND/NOR gate appears very similar to a transmission gate. Indeed, RFET based logic gates enable a very efficient new style of multitransistor transmission gates [18]. The reason is explained as follow.…”

Section: B Calculating the Effort Of The Reconfiguration Processmentioning

confidence: 99%

Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

Trommer

Heinzig

Baldauf

et al. 2015

IEEE Trans. Nanotechnology

103

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Reconfigurable silicon nanowire field-effect transistors (RFETs) combine the functionality of classical unipolar p-type and n-type FETs in one universal device. In this paper, we show devices exhibiting full symmetry between p-and n-functionality, while having identical geometry. Scaling trends and feasibility for digital circuit integration are evaluated based on TCAD simulations. The method of logical effort is applied to analyze fundamental differences in circuit topology using this unique type of multigate transistors. We introduce a set of multifunctional logic gates based on RFETs providing all basic Boolean functions, including NAND/NOR, AND/OR, and XOR/XNOR, and compared them with classical implementations. Two 1-bit full adders based on those gates are presented as an insightful example that RFETs are one possible solution to increase the system functionality. Moreover, it is shown that an asymmetric transistor layout with individual optimization of both top gates can be used to increase the speed of those circuits.

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Section: B Calculating the Effort Of The Reconfiguration Processmentioning

confidence: 99%

Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

Trommer

Heinzig

Baldauf

et al. 2015

IEEE Trans. Nanotechnology

103

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show abstract

“…Simple XOR and NAND gates have already been demonstrated on chip [6]. Moreover, RFETs deliver an increased value per building block [7]- [10], enabling the mapping of complex functions with a reduced amount of hardware, e. g. NAND and NOR function can be combined in a single 4-T logic gate.…”

Section: Circuit Design With Reconfiguralbe Fetsmentioning

confidence: 99%

“…3(c)). Although this new type of transmission gate comprises of more than two transistors per path, reconfigurable devices have been found to be very efficient in implementing transmission functions, as the device polarity is adapting to the signal at the source and drain contacts [10]. As a consequence, the RFET is always present in the preferred configuration of the respective pull-up or pulldown network.…”

Section: A Quasi-transmission-gate 1-bit Full Addermentioning

confidence: 99%

Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits

Trommer

Slesazeck

Weber

et al. 2015

EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon

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Reconfigurable silicon nanowire field effect transistors (RFETs) provide both operation modes of p-type and n-type field effect transistors in a single multigate device. This unique feature provides additional degrees of freedom in terms of circuit design and device layout. Here a device-circuit co-design study of a novel 1-bit full adder with only 20 transistors is presented. The delay of the adder is analyzed using the logical effort theory and compared to standard CMOS implementation. The effect of independent gate sizing on device and circuit characteristics will be discussed. It will be shown that asymmetric gates can be exploited to reduce the critical delay of the new adder by 15 %, although the individual device performance is kept constant.

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“…To further demonstrate the potential of the proposed technology, benchmarking of configurable dual-V T circuits was presented in [32].…”

Section: Circuit Design Opportunitiesmentioning

confidence: 99%

Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages

Zhang

Marchi

Sacchetto

et al. 2014

IEEE Trans. Electron Devices

Self Cite

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Abstract-Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential for improving circuit performance and reducing static power consumption. Here, we propose a silicon nanowire transistor with three independent GAA electrodes, demonstrating, within a unique device, a dynamic configurability in terms of both polarity and threshold voltage (V T ). This silicon nanowire transistor is fabricated using a vertically stacked structure with a top-down approach. Unlike conventional threshold voltage modulation techniques, the threshold control of this device is achieved by adapting the control scheme of the potential barriers at the source and drain interfaces and in the channel. Compared to conventional dual-threshold techniques, the proposed device does not tradeoff the leakage reduction at the detriment of the ON-state current, but only through a later turn-ON coming from a higher V T . This property offers leakage control at a reduction of loss in performance. The measured characteristic demonstrates a threshold voltage difference of ∼0.5 V between low-V T and high-V T configurations, while high-V T configuration reduces the leakage current by two orders of magnitude as compared to low-V T configuration.

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Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Cited by 79 publications

References 27 publications

Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits

Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages

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