Configurable heat generators for FPGAs

Weber, Pawel; Zagrabski, Maciej; Musz, Przemyslaw; Kȩpa, Krzysztof; Nikodem, Maciej; Wojciechowski, Bartosz

doi:10.1109/therminic.2014.6972506

Cited by 6 publications

(3 citation statements)

References 9 publications

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“…[93] proposes a thermal-aware on-line task management scheme for 3D partially reconfigurable systems. Self-heating circuits are also used to increase/decrease the die temperature [94,95,96]. Artificial/synthetic circuits are distributed in the die to heat up the die as desired.…”

Section: Prevalent Power Thermal and Fault Management Methodsmentioning

confidence: 99%

A Decision-Making Method for Run-Time Structural Adaptation Of FPGA-Based SOCS to Variations in Workload, Power Budget, Die Temperature, and Hardware Resources

Sharma

2024

Preprint

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<p>Embedded systems for application domains like robotics, aerospace, defense, etc. nowadays are developed on System-on-Chip (SoC) platforms based on Field Programmable Gate Array (FPGA) devices to support computation-intensive multi-task multi-modal dynamic workloads common for these applications. These systems therefore face the challenge to sustain the performance of their dynamic workloads in presence of variations in power budget, die temperature, and/or occurrence of hardware faults. This work proposes Run-time Structural Adaptation (RTSA) as a mechanism for mitigating these factors. One of the major contributions of this work is creation of a run-time decision-making method, ‚ÄúExplorer‚Äù, to carry out RTSA for FPGA-based SoCs and mitigate variations in the internal and external factors simultaneously. Whenever there is a change in the system‚Äôs set of constraints, Explorer selects an appropriate variant of hardware processing circuit for each active task from a large design space to form a system conÔ¨Åguration that satisÔ¨Åes each task‚Äôs performance speciÔ¨Åcation and all other system constraints. To support the practical deployment of Explorer, this work presents a method to derive run-time power consumption and die temperature estimation models for any FPGA-based device. This novel methodology of model derivation based on the FPGA platform and application running on it is another contribution of this work. The model derivation methods are formulated after detailed experimental analysis of power consumption and thermal behaviors of recent FPGA devices. Explorer can evaluate potential system conÔ¨Ågurations using the derived models to select a suitable system conÔ¨Åguration for RTSA. Experimental implementation of Explorer on the Zynq XC7Z020 SoC shows worst case execution time of 130 us, which demonstrates its suitability for RTSA for most applications associated with multi-stream computation-intensive tasks. This work also proposes an approach for automating model derivation which helps systems self-derive their model coefficients during system production and re-derive them due to changes in system platform, application, and/or environmental conditions. This significantly reduces model derivation time while avoiding any human involvement. This work thus presents the methods and models necessary to enable real systems utilizing FPGA devices to carry out RTSA and sustain their dynamic workloads amid dynamic environmental and hardware resource constraints.</p>

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Section: Prevalent Power Thermal and Fault Management Methodsmentioning

confidence: 99%

A Decision-Making Method for Run-Time Structural Adaptation Of FPGA-Based SOCS to Variations in Workload, Power Budget, Die Temperature, and Hardware Resources

Sharma

2024

Preprint

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“…e use of self-heating circuits is also observed to increase/decrease the die temperature [17][18][19].…”

Section: Literature Reviewmentioning

confidence: 99%

A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs

Sharma

Kirischian

2021

International Journal of Reconfigurable Computing

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Autonomous mobile systems nowadays deploy FPGA-based System on Programmable Chips (SoPCs) for supporting their dynamic multitask multimodal workloads. For such field-deployed systems, activation times, execution periods of tasks, and variations in environmental conditions are usually difficult to predict. These dynamic variations result in a new challenge of dynamic thermal cycling stress on the SoPC die, which can result in transient and even permanent hardware faults in the computing system. This paper proposes the approach of run-time structural adaptation (RTSA) to mitigate dynamic thermal cycling stress on the SoPC dies. RTSA assumes the tasks to have multiple implementation variants, called Application Specific Processing (ASP) circuit variants, which vary in hardware resources, operating frequency, and power consumption. Dynamically reconfiguring appropriate ASP circuit variants of tasks allow systems to maintain their die temperature in the desired range while taking into account variations in power budget and modes of operation. This means the essence of RTSA is a decision-making mechanism which can select at run-time, a suitable system configuration (set of ASP circuit variants of active tasks), whenever needed, to meet the die temperature constraints. To do so, run-time die temperature prediction for potential system configurations using an estimation model is required. This paper presents a generic method to derive an analytical model for any SoPC that can estimate the die temperature in real time and thus support the decision-making mechanism. To develop this method, the thermal behavior of SoPC die under different task scenarios is studied and relation of die temperature to frequency, resource utilization, and power consumption is analyzed. An RTSA-enabled experimental platform is set up on Xilinx Zynq XC7Z020 SoPC for this purpose. Experimental results also demonstrate that the proposed method can be used to derive a model in run-time, thus enabling systems to self-derive and dynamically update the model in run-time.

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“…The first one is by designing on-chip heating elements. There are work [46], [47] that proposed to use re-configurable blocks with high switching activities or small ring oscillators to generate heat for thermal-aware testing on FPGA. The results were promising and showed a very wide range of achievable temperatures by small heating blocks with a very high accuracy (variations are within ±1°C) [47].…”

Section: Clash: Cross-layer Accelerated Self-healing Implementationsmentioning

confidence: 99%

Implications of accelerated self-healing as a key design knob for cross-layer resilience

Guo

Stan

2017

Integration

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In this paper we propose a cross-layer accelerated self-healing (CLASH) system which "repairs" its wearout issues in a physical sense through accelerated and active recovery, by which wearout can be reversed while actively applying several accelerated self-healing techniques, such as high temperature and negative voltages. Different from previous solutions of coping with wearout issues (e.g. BTI) by "tolerating", "slowing down" or "compensating", which still leave the irreversible (permanent) wearout component unchecked, the proposed solution is able to fully avoid the irreversible wearout through periodic rejuvenation, and this is inspired by the explored frequency dependent behaviors of wearout and (accelerated and active) recovery based on measurements on FPGAs. We demonstrate a case where the chip can always be brought back to the fresh status by employing a pattern of 31-hour regular operation (under room temperature and nominal voltage) followed by a 1-hour accelerated selfhealing (under high temperature and negative voltage). The proposed system integrates the notions of accelerated self-healing across multiple layers of the system stack. At the circuit level, a negative voltage generator and heating elements are designed and implemented; at the architecture level, the core can be allocated in a way such that the dark silicon or redundant resources can be healed by active elements; at the system level, right balance of stress and accelerated/active recovery can be employed by the system scheduler to fully mitigate the wearout; various wearout sensors act as the media between different layers. Overall, these techniques work together to guarantee that the whole system performs for more of the time at higher levels of performance and power efficiency by fully taking advantage of the extra opportunities enabled by the accelerated self-healing.

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Configurable heat generators for FPGAs

Cited by 6 publications

References 9 publications

A Decision-Making Method for Run-Time Structural Adaptation Of FPGA-Based SOCS to Variations in Workload, Power Budget, Die Temperature, and Hardware Resources

A Decision-Making Method for Run-Time Structural Adaptation Of FPGA-Based SOCS to Variations in Workload, Power Budget, Die Temperature, and Hardware Resources

A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs

Implications of accelerated self-healing as a key design knob for cross-layer resilience

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