Configurable links for runtime adaptive on-chip communication

Faruque, Mohammad Abdullah Al; Ebi, Thomas; Henkel, Jörg

doi:10.1109/date.2009.5090667

Cited by 31 publications

(19 citation statements)

References 13 publications

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“…[50,59], and [52]), reconfigurable links (e.g. Direction/Bandwidth of links [43]), reconfigurable PEs, and reconfigurable router (e.g. [45], and [55]).…”

Section: Design Methodologiesmentioning

confidence: 99%

“…The authors also implemented a cycle-accurate simulator for the proposed NoC. Al Faruque et al [43] proposed novel adaptive routing algorithm (called weight-XY) and adaptive buffer allocation scheme. The proposed adaptive buffer allocation scheme can re-assign a certain number of buffer blocks to different virtual channel for each of output ports of a router on-demand.…”

Section: Reconfigurable Parameters Of Nocmentioning

confidence: 99%

“…The purpose of lanes is similar to that of virtual channels in packet-switched router. Al Faruque et al [43] presented a novel configurable link which can change its supported bandwidth on-demand at run-time for the adaptive on-chip communication architecture. In [55], Nicopoulos et al introduced a novel unified buffer structure, called the dynamic Virtual Channel Regulator (ViChaR), which dynamically can allocate VC and buffer resources according to the network traffic conditions.…”

Section: Reconfigurable Parameters Of Nocmentioning

confidence: 99%

See 2 more Smart Citations

A Survey on Reconfigurable System-on-Chips

Nguyen

Le-Van

Tran

2018

REV J. Electron. Commun.

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Abstract-The requirements for high performance and low power consumption are becoming more and more inevitable when designing modern embedded systems, especially for the next generation of multi-mode multimedia or communication standards. Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in comparison with the conventional architectures. The unique characteristic of such systems is the integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip. This paper analyzes and emphasizes the key research trends of reconfigurable System-on-Chips (SoCs). Firstly, the emerging hardware architecture of SoCs is highlighted. Afterwards, the key issues of designing reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips. Finally, some state-of-the-art reconfigurable SoCs are briefly discussed.

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“…[50,59], and [52]), reconfigurable links (e.g. Direction/Bandwidth of links [43]), reconfigurable PEs, and reconfigurable router (e.g. [45], and [55]).…”

Section: Design Methodologiesmentioning

confidence: 99%

Section: Reconfigurable Parameters Of Nocmentioning

confidence: 99%

Section: Reconfigurable Parameters Of Nocmentioning

confidence: 99%

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A Survey on Reconfigurable System-on-Chips

Nguyen

Le-Van

Tran

2018

REV J. Electron. Commun.

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“…However, both techniques need a root node to monitor network traffic and perform path allocation in runtime. Al Faruque et al [7] apply centralized configuration on directions of 2X-Links to implement bidirectional transmission. Lan et al [8] propose selfreconfigurable bidirectional channels with direction control protocol to satisfy bandwidth requirement.…”

Section: Related Workmentioning

confidence: 99%

HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip

Wei

Liu

Sun

et al. 2016

IEICE Electron. Express

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With a growing number of cores integrated in a single chip, the efficiency of inter-core direct memory access (DMA) transfers has an increasingly significant impact on the overall performance of parallel applications running on network-on-chip (NoC) processors. In this paper we propose HyDMA, a low-latency inter-core DMA approach based on a hybrid packetcircuit switching NoC. With dynamic setup and lengthening of circuit channels composing of bidirectional links, HyDMA can achieve both high flexibility of packet switching and low communication latency of circuit switching for concurrent DMA transfers. Experimental results prove HyDMA exhibits high efficiency with marginal hardware overhead.

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“…This is motivated by the observation that, between two routers, quite often one uni-directional link may be overflowed with heavy traffic while the link for the opposite direction remains idle [100][101][102]. The inefficient link bandwidth usage in uni-directional NoC may limit the system latency and throughput.…”

Section: Introductionmentioning

confidence: 99%

High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization

Qian¹

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TABLE OF CONTENTS Title Page i Authorization Page ii Signature Page iiiAcknowledgments iv Table of Contents v List of Figures ix List of Tables xiiiAbstract xiv Therefore, fast and accurate analytical models for NoC-based multicore performance evaluation are strongly desired to better explore the design space. For this purpose, we propose a machine learning based latency regression model to evaluate the NoC designs with respect to different configurations before the system is built or taped-out. Then, for high performance NoC designs, we tackle one of the most important problems, i.e., the routing algorithms design with different design constraints and objectives. For avoiding temperature hotspots, a thermal-aware routing algorithm is proposed to achieve an even temperature profile for application-specific Network-on-chips (NoCs). For improving the reliability, a routing algorithm to achieve maximum performance under fault is proposed. Finally, in the architecture level, we propose two new NoC structures using bi-directional links for the performance optimization. In particular, we propose a flit-level speedup scheme to enhance the network-on-chip(NoC) performance utilizing bidirectional channels. In addition to the traditional efforts on allowing flits of different packets using the idling internal and external bandwidth of the bidirectional channel, our proposed flit-level speedup scheme also allows flits within the same packet to be transmitted simultaneously on the bi-directional channel.We also propose a flexible NoC architecture which takes advantage of a dynamic distributed routing algorithm and improves the NoC communication performance with minimal energy overhead. This proposed NoC architecture exploits the selfreconfigurable bidirectional channels to increase the effective bandwidth and uses express virtual paths, as well as localized hub routers, to bypass some intermediate nodes at run time in the network. From the simulation results on both synthetic traffic and real workload traces, significantly performance improvement in terms of latency and throughput can be achieved.

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Configurable links for runtime adaptive on-chip communication

Cited by 31 publications

References 13 publications

A Survey on Reconfigurable System-on-Chips

A Survey on Reconfigurable System-on-Chips

HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip

High performance network-on-chips (NoCs) design : performance modeling, routing algorithm and architecture optimization

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