Configurable Quasi-Optimal Sphere Decoding for Scalable MIMO Communications

Abstract

Sphere Decoding (SD) enables real-time quasioptimal symbol detection for Multiple-Input Multiple-Output (MIMO) communication systems via custom circuit accelerators. Configurable SDs allow accelerator cost to be balanced with detection accuracy for the most constrained MIMO environments, such as power-constrained Internet-of-Things (IoT) scenarios. However this high detection accuracy comes at high accelerator cost. This paper proposes a novel configurable SD which addresses this issue. A Robust Bounded Spanning with Fast Enumeration (R-BSFE) approach employs novel strategies for channel matrix pre-processing and symbol enumeration to maintain quasi-ML accuracy whilst reducing complexity by up to 74%. This enables accelerators for 802.11n on Xilinx FPGA with significantly lower cost and higher throughput. To the best of the authors' knowledge, the accelerators produced are the highest performance, lowest cost quasi-ML SD accelerators on record.

Joint High-Dimensional Soft Bit Estimation and Quantization using Deep Learning

“…In the soft-output version [20], multiple candidate solutions are used to estimate log-likelihoods. A drawback of this class of algorithms is the need for specialized hardware to fit into tight latency budgets in 5G and beyond scenarios [21]. To address latency, recent work combines sphere decoding with deep learning for search radius and branch prediction [22].…”

Efficient Massive MIMO Detection for M-QAM Symbols

“…Sphere decoder (SD) can achieve near-ML performance while requiring less computational complexity than ML detectors. Its computational complexity, however, is inconsistent with the large-scale MIMO problem [ 3 ]. Belief propagation (BP) detectors provide the soft output in an iterative process via a factor graph and suffer less local minimum problems than other algorithms.…”

Sub-optimal Deep Pipelined Implementation of MIMO Sphere Detector on FPGA

“…The simulated result shows a maximum throughput of 2.2 Gbps, which so far is the fastest hardware of FSD implementation in our record. K-best is another popular SD accelerator architecture and has been actively studied recently [13][14][15][16][17][18][19][20][21][22]. The K-Best SD is based on breadth-first search, which considers only the best (K) candidates at each level to be passed to the next level of the search tree.…”

“…Thus, ML could be considered a special case of K-best with a sufficiently large K [13]. The conventional K-best sphere detectors use the same K value at all levels [13][14][15][16][17][18], while recent developments offer more flexible and efficient designs [19][20][21][22]. Among those, several practical K-Best SD has been prototyped on hardware [16,17,[19][20][21][22]28] that show advantages over FSD in both complexity and throughput.…”