Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems

Abstract

Abstract-In spite of the increasing success of reconfigurable hardware, the dynamic reconfiguration can introduce important overheads, both in terms of energy consumption and time, especially when configurations are fetched from an external memory. In order to address this problem, this article presents a configuration memory hierarchy including two on-chip memory modules with different access time and energy consumption features. In addition, we have developed two configuration mapping algorithms that take advantage of these memories to reduce the system energy consumption, while increasing its performance. The first algorithm has been optimized for systems with reduced dynamic behavior, hence it optimizes the system for each given set of tasks. The second algorithm targets dynamic systems where the active tasks change unpredictably. Thus, its objective is also to decrease the pressure on the on-chip memories to reduce capacity conflicts.The presented results will demonstrate that, with the proper management, our configuration memory hierarchy leads to an energy consumption reduction up to 81% with respect to fetching the configurations from the external memory, while keeping the system performance very close to the ideal upperbound one.

R3TOS-Based Integrated Modular Space Avionics for On-Board Real-Time Data Processing

“…For a case study CORDIC circuit, an average of 34.5% of power saving was obtained using the proposed task wrapper. In addition, the proposed task reuse scheme in chapter 5 also has the potential to reduce power consumption as memory accesses associated with task configuration is an energy intensive operation [124]. Low power computation is a major goal of many system designers.…”

On-Line Reusing-Based Scheduling Algorithm for 2-Dimensional Tasks in Reconfigurable Hardware

“…So based on this assumption, their algorithm pre-fetches tasks as soon as possible and two metrics are calculated for it, priority of the tasks and placement decision to avoid conflicts between tasks. Some memory hierarchy models also are introduced to reduce the configuration overhead which in [13] two onchip memories with different access time are discussed and efficient mapping algorithms with respect to energy consumption and access latency features are proposed. [14] is recent scheduling method based on our works which mitigated the configuration overhead.…”

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex‐5 field‐programmable gate array

“…Another option to reduce the reconfiguration overhead is to customise the memory resources used to store the configurations. For instance, Clemente et al [16] propose to include heterogeneous on‐chip memory modules, ones optimised for performance and others optimised for low power. With this approach, the designer can explore different power/performance reconfiguration tradeoffs.…”