Congestion analysis for global routing via integer programming

Shojaei,; Davoodi,; Linderoth,

doi:10.1109/iccad.2011.6105337

Cited by 26 publications

(35 citation statements)

References 20 publications

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“…In this section we describe our routing framework, which is an extension of CGRIP [13]. By extending from CGRIP, our framework can also account for the same complicating factors-varying wire size and spacing at different metal layers, routing blockages, and virtual pins-as CGRIP.…”

Section: Routing Frameworkmentioning

confidence: 99%

“…In this extension, we set this parameter to be of maximum resolution. For details about CGRIP, please refer to [13]. Extensions: We now discuss how individual steps in CGRIP are revised to handle the new IP formulation (IP-LC) and the local congestion models with non-uniform gcell sizes.…”

Section: Routing Frameworkmentioning

confidence: 99%

“…2) Initial Solution: To create an initial solution, multi-terminal nets are decomposed into two-terminal subnets according to their Minimum Spanning Tree (MSTs), as in [4,12,13]. The same decomposition is used during the procedure to generate non-uniform gcells which was explained in Section 2.…”

Section: Routing Frameworkmentioning

confidence: 99%

“…Along this line, CGRIP [13] is a flexible GR tool that can handle arbitrary routing blockages and virtual pins, and varying wire sizes and spacings. However, CGRIP does not account for local congestion effects.…”

Section: Introductionmentioning

confidence: 99%

“…The practical realization is based on integration with the CGRIP congestion analysis tool [13], revising its functionality to suit the goals of this research effort.…”

Section: Introductionmentioning

confidence: 99%

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Planning for local net congestion in global routing

Shojaei

Davoodi

Linderoth

2013

Proceedings of the 2013 ACM International Symposium on Physical Design

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Local nets are a major contributing factor to mismatch between the global routing (GR) and detailed routing (DR) stages. A local net has all its terminals inside one global cell (gcell) and is traditionally ignored during global routing. This work offers two contributions in order to estimate and manage the local nets at the GR stage. First, a procedure is given to generate gcells of non-uniform size in order to reduce the number of local nets and thus the cumulative error associated with ignoring or approximating them. Second, we approximate the resource usage of local nets at the GR stage by introducing a capacity for each gcell in the GR graph. With these two complementary approaches, we offer a mathematical model for the congestion-aware GR problem that captures local congestion with non-uniform gcells along with other complicating factors of modern designs including variable wire sizes, routing blockages, and virtual pins. A practical routing procedure is presented based on the mathematical model that can solve large industry instances. This procedure is integrated with the CGRIP congestion analysis tool. In the experiments, we evaluate our techniques in planning for local nets during GR while accounting for other sources of congestion using the ISPD11 benchmarks.

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Section: Routing Frameworkmentioning

confidence: 99%

Section: Routing Frameworkmentioning

confidence: 99%

Section: Routing Frameworkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…The practical realization is based on integration with the CGRIP congestion analysis tool [13], revising its functionality to suit the goals of this research effort.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Planning for local net congestion in global routing

Shojaei

Davoodi

Linderoth

2013

Proceedings of the 2013 ACM International Symposium on Physical Design

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Effective regularity extraction and placement techniques for datapath‐intensive circuits

Wang

Shin

2017

IET Circuits, Devices & Systems

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Regular structures, like datapath, are important components of integrated circuits. Datapath logic is usually placed with high regularity and compactness for higher performance by using manual placement. The authors propose effective datapath regularity extraction and placement (DREP) techniques which simultaneously place datapath logic and random logic. This method detects datapath logic and effectively formats regular datapath structures while optimizing the order of functional stages and placement of datapath blocks. Moreover, the datapath structures are further optimized by using bit-slice order adjustment and partitioning techniques during global placement. Partitioning of a big datapath macro greatly increases the placement flexibility, since partitioned sub-blocks of the datapath macro can be optimally placed with other blocks. A new effective method is also suggested to decide the block to be partitioned and the granularity of partitioning. Similar to the manual placement results, the datapath logic is regularly placed and the datapath cells are aligned well, vertically or horizontally by the DREP techniques. When compared with the state-of-the-art works, the experimental results show that the new techniques produce significantly better results than other methods in terms of half perimeter wire length, Steiner wire length, and routability, measured from the detail routing results.

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Effective datapath logic extraction techniques using connection vectors

Wang

Yeo

Shin

2019

IET Circuits, Devices & Systems

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Datapath macros are essential components of integrated circuits. The high regularity of datapaths allows compact layout design during placement. In some cases, datapath macros are manually pre-designed and pre-placed. However, datapath macros are frequently mixed with other circuits and they need to be extracted to capitalise on their regularity. In this study, the cells of a given circuit are accurately classified based on their size and pin information, and novel connection vectors to represent aspects of the connectivity among the cells have been proposed. By using the connection vectors of the cells, the similarity of connections is evaluated to extract potential datapath stages that constitute functional steps of a datapath. Two new efficient datapath logic extraction techniques (EDLETs) have been implemented based on the connection vectors for extracting potential datapaths in the circuit. One is the procedure-based method, and the other is the machine learning-based method. When compared with state-of-the-art methods, the experiments show that both the procedure-based and the learning-based methods proposed in this study efficiently extract potential datapaths from the Modified International Symposium on Physical Design (MISPD) 2011 Datapath Benchmark Suite. The extraction results of the proposed EDLET can be forwarded to a datapath placement tool for placing datapaths with a regular structure.

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Congestion analysis for global routing via integer programming

Cited by 26 publications

References 20 publications

Planning for local net congestion in global routing

Planning for local net congestion in global routing

Effective regularity extraction and placement techniques for datapath‐intensive circuits

Effective datapath logic extraction techniques using connection vectors

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