2020
DOI: 10.1109/tdsc.2017.2779780
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Connecting the Dots: Privacy Leakage via Write-Access Patterns to the Main Memory

Abstract: Abstract-Data-dependent access patterns of an application to an untrusted storage system are notorious for leaking sensitive information about the user's data. Previous research has shown how an adversary capable of monitoring both read and write requests issued to the memory can correlate them with the application to learn its sensitive data. However, information leakage through only the write access patterns is less obvious and not well studied in the current literature. In this work, we demonstrate an actua… Show more

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Cited by 6 publications
(5 citation statements)
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References 19 publications
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“…Such operations may inadvertently create recognizable patterns in the eyes of the passive adversary. Research has shown that by only observing the memory change over time, attackers can recover sensitive information about the unencrypted data [60]. C4: Memory splicing and replaying attacks.…”
Section: Challengesmentioning
confidence: 99%
“…Such operations may inadvertently create recognizable patterns in the eyes of the passive adversary. Research has shown that by only observing the memory change over time, attackers can recover sensitive information about the unencrypted data [60]. C4: Memory splicing and replaying attacks.…”
Section: Challengesmentioning
confidence: 99%
“…Ref. [19] demonstrates privacy leakage from the main memory using the Montgomery's ladder technique to send a 128-byte message with a 64-byte secret exponent, where the PCILeech can obtain all the secret bits.…”
Section: Dma Attackmentioning
confidence: 99%
“…Research has also shown that routers in the on-chip networks expose application traffic traces [23] that leads to information leakage. Furthermore, information can also be leaked via off-chip memory-based timing channels, where the adversary monitors memory latencies of the victim application [48], [49]. Prior works have explored various mitigation mechanisms, such as employing time-multiplexed memory bandwidth reservation [29], or adopting a non-interference memory controller [50].…”
Section: B Protecting Non-speculative Microarchitecture Statementioning
confidence: 99%