Connectivity-based multichip module repair

Choi, Minsu; Park, N.; Meyer, F.J.; Lombardi, Fabrizio

doi:10.1109/prdc.2001.992675

Cited by 3 publications

(2 citation statements)

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“…[6] has addressed the challenges in testing core-based system ICs by describing and comparing the differences between traditional test method and core-based test method. [7] has proposed a repair method based on the connectivity of the chips on MCM (Multichip Module) in which yield degradation due to neighboring chips and interconnect structure was modeled and analyzed. Several MCM repair scheduling strategies based on the number of interconnections and the number of neighboring chips has been shown in [7], and it has evaluated the impact of connectivity-based repair scheduling on the overall yield of MCMs.…”

Section: Introductionmentioning

confidence: 99%

“…[7] has proposed a repair method based on the connectivity of the chips on MCM (Multichip Module) in which yield degradation due to neighboring chips and interconnect structure was modeled and analyzed. Several MCM repair scheduling strategies based on the number of interconnections and the number of neighboring chips has been shown in [7], and it has evaluated the impact of connectivity-based repair scheduling on the overall yield of MCMs. In [8] the reliability of SoC design when bus errors affect the SoC interconnection architecture has been addressed and an approach to enhance the error detection and correction mechanism of the system bus has been proposed based on the concept of distributed bus guardians.…”

Section: Introductionmentioning

confidence: 99%

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Spare Line Borrowing Technique for Distributed Memory Cores in SoC

Jang

Choi²,

Park³

et al.

2005 IEEE Instrumentationand Measurement Technology Conference Proceedings

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In this paper, a new architecture of distributed embedded memory cores for soc is proposed and an effective memory repair method by using the proposed Spare Line Borrowing (software-driven reconfiguration) technique is investigated. It is known that faulty cells in memory core show spatial locality, also known as fault clustering. This physical phenomenon tends to occur more oft en as deep submicron technology advances due to defects that span multiple circuit elements and sophisticated circuit design. The combination of new architecture & repair method proposed in this paper ensures fault tolerance enhancement in Soc, especially in case of fault clustering. This fault tolerance enhancement is obtained through optimal redundancy utilization: Spare redundancy in a fault-resistant memory core is used to fix the fault in a fault prone memory core. The effect of Spare Line Borrowing technique on the reliability of distributed memory cores is analyzed through modeling and extensive parametric simulation.

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Section: Introductionmentioning

confidence: 99%