Consistent, durable, and safe memory management for byte-addressable non volatile main memory

Moraru, Iulian; Andersen, David G.; Kaminsky, Michael; Tolia, Niraj H.; Ranganathan, Parthasarathy; Binkert, Nathan

doi:10.1145/2524211.2524216

Cited by 87 publications

(40 citation statements)

References 32 publications

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“…Strictly linearizable examples include trees [27,29], file systems [9], and hash maps [26]. Buffered strictly linearizable data structures also exist [23], and some libraries explicitly enable their construction [4,6]. Durably (but not strictly) linearizable data structures are a comparatively recent innovation [20].…”

Section: Practical Applicationsmentioning

confidence: 99%

Linearizability of Persistent Memory Objects Under a Full-System-Crash Failure Model

Izraelevitz

Mendes

Scott

2016

Lecture Notes in Computer Science

122

208

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This paper provides a theoretical and practical framework for crash-resilient data structures on a machine with persistent (nonvolatile) memory but transient registers and cache. In contrast to certain prior work, but in keeping with "real world" systems, we assume a full-system failure model, in which all transient state (of all processes) is lost on a crash. We introduce the notion of durable linearizability to govern the safety of concurrent objects under this failure model and a corresponding relaxed, buffered variant which ensures that the persistent state in the event of a crash is consistent but not necessarily up to date.At the implementation level, we present a new "memory persistency model," explicit epoch persistency, that builds upon and generalizes prior work. Our model captures both hardware buffering and fully relaxed consistency, and subsumes both existing and proposed instruction set architectures. Using the persistency model, we present an automated transform to convert any linearizable, nonblocking concurrent object into one that is also durably linearizable. We also present a design pattern, analogous to linearization points, for the construction of other, more optimized objects. Finally, we discuss generic optimizations that may improve performance while preserving both safety and liveness.

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Section: Practical Applicationsmentioning

confidence: 99%

Linearizability of Persistent Memory Objects Under a Full-System-Crash Failure Model

Izraelevitz

Mendes

Scott

2016

Lecture Notes in Computer Science

122

208

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“…As such, persistent memory can dramatically boost the performance of applications that require high reliability demand, such as databases and file systems, and enable the design of more robust systems at high performance. As a result, persistent memory has recently drawn significant interest from both academia and industry [13,14,29,30,37,54,60,66,70,71,88,90]. Recent works [54,92] even demonstrated a persistent memory system with performance close to that of a system without persistence support in memory.…”

Section: Introductionmentioning

confidence: 99%

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Byte-addressable nonvolatile memories promise a new technology, persistent memory, which incorporates desirable attributes from both traditional main memory (byte-addressability and fast interface) and traditional storage (data persistence). To support data persistence, a persistent memory system requires sophisticated data duplication and ordering control for write requests. As a result, applications that manipulate persistent memory (persistent applications) have very different memory access characteristics than traditional (non-persistent) applications, as shown in this paper. Persistent applications introduce heavy write traffic to contiguous memory regions at a memory channel, which cannot concurrently service read and write requests, leading to memory bandwidth underutilization due to low bank-level parallelism, frequent write queue drains, and frequent bus turnarounds between reads and writes. These characteristics undermine the high-performance and fairness offered by conventional memory scheduling schemes designed for non-persistent applications.Our goal in this paper is to design a fair and high-performance memory control scheme for a persistent memory based system that runs both persistent and non-persistent applications. Our proposal, FIRM, consists of three key ideas. First, FIRM categorizes request sources as non-intensive, streaming, random and persistent, and forms batches of requests for each source. Second, FIRM strides persistent memory updates across multiple banks, thereby improving bank-level parallelism and hence memory bandwidth utilization of persistent memory accesses. Third, FIRM schedules read and write request batches from different sources in a manner that minimizes bus turnarounds and write queue drains. Our detailed evaluations show that, compared to five previous memory scheduler designs, FIRM provides significantly higher system performance and fairness.

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“…And current solutions to the write ordering and atomicity problems are either relying on some newly-proposed hardware primitives, such as atomic 8-byte writes and epoch barriers [129], [205], [212], or leveraging existing hardware primitives, such as cache modes (e.g., write-back, write-combining), memory barriers (e.g., mfence), cache line flush (e.g., clflush) [128], [130], [213], which, however, may incur non-trivial overhead. General libraries and programming interfaces are proposed to expose NVRAM as a persistent heap, enabling NVRAM adoption in an easy-to-use manner, such as NV-heaps [214], Mnemosyne [215], NVMalloc [216], and recovery and durable structures [213], [217]. In addition, file system support enables a transparent utilization of NVRAM as a persistent storage, such as Intel's PMFS [218], BPFS [205], FRASH [219], ConquestFS [220], SCMFS [221], which also take advantage of NVRAM's byte addressability.…”

Section: Nvrammentioning

confidence: 99%

In-Memory Big Data Management and Processing: A Survey

Zhang

Chen

Ooi

et al. 2015

IEEE Trans. Knowl. Data Eng.

362

156

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Growing main memory capacity has fueled the development of in-memory big data management and processing. By eliminating disk I/O bottleneck, it is now possible to support interactive data analytics. However, in-memory systems are much more sensitive to other sources of overhead that do not matter in traditional I/O-bounded disk-based systems. Some issues such as fault-tolerance and consistency are also more challenging to handle in in-memory environment. We are witnessing a revolution in the design of database systems that exploits main memory as its data storage layer. Many of these researches have focused along several dimensions: modern CPU and memory hierarchy utilization, time/space efficiency, parallelism, and concurrency control. In this survey, we aim to provide a thorough review of a wide range of in-memory data management and processing proposals and systems, including both data storage systems and data processing frameworks. We also give a comprehensive presentation of important technology in memory management, and some key factors that need to be considered in order to achieve efficient in-memory data management and processing.

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Consistent, durable, and safe memory management for byte-addressable non volatile main memory

Cited by 87 publications

References 32 publications

Linearizability of Persistent Memory Objects Under a Full-System-Crash Failure Model

Linearizability of Persistent Memory Objects Under a Full-System-Crash Failure Model

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

In-Memory Big Data Management and Processing: A Survey

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