Consistent Noise Models for Analysis and Design of CMOS Circuits

Arnaud, Alfredo; Galup-Montoro, Carlos

doi:10.1109/tcsi.2004.835028

Cited by 43 publications

(29 citation statements)

References 16 publications

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“…Therefore, here only flicker noise has been considered to introduce the concept developed. There exist numerous models for flicker noise in the MOS transistor [2][3][4][5][6][7][8][9][10]. In accordance with the most popular model [10], the flicker noise due to a MOS transistor can be lumped as a voltage source at the gate and is given by…”

Section: Noise Model For Mostmentioning

confidence: 99%

Figure‐of‐Merit‐Based Area‐Constrained Design of Differential Amplifiers

Agarwal

Shekhar

2008

VLSI Design

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A new methodology based on the concept of figure of merit under area constraints is described for designing optimum performance differential amplifiers. First a figure of merit is introduced that includes the three performance parameters, namely, input-referred noise, differential dc gain, and unity-gain bandwidth. Expressions for these parameters have been derived analytically and finally arrived at an expression for the figure of merit. Next it is shown how these performance parameters vary with the relative allocation of the total available area between the input and load transistors. The figure of merit peaks at a certain value of relative area allocation in the range of 60% to 80% of the available area to the input transistors. The peak value of figure of merit is a function of area. However, it is independent of biasing current (and, therefore, power consumption) subject to the minimum current (and, therefore, a minimum power) required to keep all the transistors biased in the saturation region. The peak figure of merit and minimum power required to achieve the peak figure of merit are also plotted as a function of area. These analyses help in synthesizing optimal differential amplifier circuit designs under area constraints.

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Section: Noise Model For Mostmentioning

confidence: 99%

Figure‐of‐Merit‐Based Area‐Constrained Design of Differential Amplifiers

Agarwal

Shekhar

2008

VLSI Design

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“…The main sources of electrical noise in the frequency span of biological signals -apart from coupling noise-are thermal and flicker noise of the circuit elements at the input stage. For a MOS transistor, thermal noise current model is in general not questioned its PSD being (the PSD of the noise current in parallel with the transistor) [5]:…”

Section: Introductionmentioning

confidence: 99%

“…Where B k is the Boltzmann's constant, T the absolute temperature, m g is the transistor's transconductance, n ≈ 1 is the slope factor, γ = 2, or 8/3 in strong an weak inversion respectively [5]. Although some existing flicker noise models may cause misleading results, as pointed in [5] the application of the empirical model for flicker noise:…”

Section: Introductionmentioning

confidence: 99%

“…Although some existing flicker noise models may cause misleading results, as pointed in [5] the application of the empirical model for flicker noise:…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

On the design of ultra low noise amplifiers for ENG recording

Arnaud

Bremermann

Gak

et al. 2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

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Due to the extremely low amplitude of the input signals, the design of electro-neurgo-graph (ENG) amplifiers normally involves special care for flicker and thermal noise reduction. The task becomes really challenging in the case of implantable devices, because power consumption is restricted to few tens µW. In this paper, two different circuit techniques aimed to reduce flicker and thermal noise, in ultra-low noise amplifiers for implantable electronics are demonstrated. In both cases circuit design and measurement results are presented, showing an excellent performance in circuit simplicity, and noise to power consumption trade-off. The first circuit is a very simple G m -C chopper low-pass amplifier for flicker noise cancellation. It consumes only 28mW, with a measured input referred noise and offset of 1.2 Hz nV , and 2.5µV, respectively. For the reduction of thermal noise with minimum power consumption, in the second circuit, a ultra-low noise amplifier, a energy-efficient DC-DC downconverter, and low voltage design techniques are combined. Measured input referred noise in this case was 5,5 Hz nV at only 380µW power consumption. Both circuits were fabricated in a 1,5 micron technology.

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Integrated potentiostat for detection of Chagas disease

Agis

Torres

Gak

et al. 2018

Circuit Theory & Apps

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The design of a low-power-integrated potentiostat that measures electric current intended for a Chagas disease detection application is presented. This circuit can generate and measure currents from 1 to 10 μA with a relative error under 5%. The remaining part of the circuit consumes only 1.5 μA. The circuit was designed using the 0.6 μm XC06 technology from the X-FAB, with a total silicon area of 0.24 mm 2 (without pads).

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Consistent Noise Models for Analysis and Design of CMOS Circuits

Cited by 43 publications

References 16 publications

Figure‐of‐Merit‐Based Area‐Constrained Design of Differential Amplifiers

Figure‐of‐Merit‐Based Area‐Constrained Design of Differential Amplifiers

On the design of ultra low noise amplifiers for ENG recording

Integrated potentiostat for detection of Chagas disease

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