Constant-Resistance CMOS Input Sampling Switch for GSM/WCDMA High Dynamic Range $\Delta \Sigma$ Modulators

Adeniran, O.A.; Demosthenous, Andreas

doi:10.1109/tcsi.2008.924883

Cited by 14 publications

(6 citation statements)

References 39 publications

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“…The noise is received by analog substrate contacts and signal nodes through resistive and capacitive coupling, which reduces the circuit performance by direct injection or indirectly by altering transistor threshold voltages [16]. To reduce problems with SSN, the circuits are commonly designed with separate analog and digital power supply lines, physical separation between noisy and noise prone components, and differential analog circuit architecture [17], [18].…”

Section: B Effect Of Ssn In Analog Circuitsmentioning

confidence: 99%

Reduction of Substrate Noise in Sub Clock Frequency Range

Sherazi

Asif

Backenius³

et al. 2010

IEEE Trans. Circuits Syst. I

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Abstract-We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130-nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where an 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.Index Terms-Flip-flops, integrated circuit noise, mixed analogdigital integrated circuits, simultaneous switching noise, substrate noise.

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Section: B Effect Of Ssn In Analog Circuitsmentioning

confidence: 99%

Reduction of Substrate Noise in Sub Clock Frequency Range

Sherazi

Asif

Backenius³

et al. 2010

IEEE Trans. Circuits Syst. I

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“…The consequent reduction of available voltage room between power rails is then compensated by specific circuit techniques, which try to optimize internal signal headroom allocation against device non-linearities. Examples of lowvoltage SC design strategies are: rail-to-rail operation [1], bulk-driven inputs [2], [3], internal supply multipliers to drive critical switches [4], [5], inverter-based amplifiers [6], [7], and switched-OpAmps (SOAs) for replacing critical switches [8]. In practice, low-voltage SC techniques usually can only S. Sutula is with Broadcom Ltd., Barcelona, Spain.…”

Section: Introductionmentioning

confidence: 99%

Variable-Mirror Amplifier: A New Family of Process-Independent Class-AB Single-Stage OTAs for Low-Power SC Circuits

Sutula

Dei

Terés

et al. 2016

IEEE Trans. Circuits Syst. I

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This paper presents a new family of Class-AB operational transconductance amplifier (OTA) circuits based on single-stage topologies with non-linear current amplifiers. The proposed variable-mirror amplifier (VMA) architecture is mainly characterized by generating all Class-AB current in the output transistors only, by exhibiting very low sensitivity to both technology and temperature deviations, and by avoiding the need for any internal frequency-compensation mechanism. Hence, this family of OTAs is well-suited for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast onoff operation and multi-decade load-capacitance specifications. Analytical expressions valid in all regions of operation are presented to minimize VMA settling time in discrete-time circuits. Also, a complete OTA design example integrated in 0.18µm 1P6M MiM 1.8V CMOS technology is supplied with detailed simulation and experimental results. Compared to resistor-free state-of-art Class-AB OpAmp and OTA literature, the proposed architecture returns the highest measured figure-of-merit value.

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“…Thus, the threshold voltages of MOSFET devices are relatively high for the given supply voltage ranges even for future CMOS processes. Also for older CMOS process technologies which are popular for most of radio-frequency (RF) integrated circuit and transceiver manufacturers, problems to design high-speed low-voltage circuits are worse because low-threshold-voltage devices are unavailable [3].…”

Section: Introductionmentioning

confidence: 99%

Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

Sarafi

A’ain

Abbaszadeh

2015

Circuits Syst Signal Process

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Sampling switches have a dominant role in switched-capacitor circuits and analog-to-digital convertors. Since they act as input gates, their nonlinearities directly degrade the quality of the input signals. The scaling-down trend of CMOS technology and increasing demands for high-speed and power-efficient circuits pose design challenge in high-speed sampling switches for low-voltage applications. To address this issue, an optimized CMOS switch is proposed in this paper consisting of a bootstrapped NMOS switch and a boosted PMOS switch as a transmission gate. By utilizing this technique, the nonlinearity resulting from the threshold voltage variation (body effect) of NMOS switch is mitigated, considerably. To evaluate the proposed switch, it is designed in 0.18 μm CMOS process technology. According to the obtained simulation results, this switch can achieve total harmonic distortion of −78.81 and −62.99 dB in 100 MS/s at V dd = 1 Volt and 50 MS/s at V dd = 0.8 V, respectively.

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Constant-Resistance CMOS Input Sampling Switch for GSM/WCDMA High Dynamic Range $\Delta \Sigma$ Modulators

Cited by 14 publications

References 39 publications

Reduction of Substrate Noise in Sub Clock Frequency Range

Reduction of Substrate Noise in Sub Clock Frequency Range

Variable-Mirror Amplifier: A New Family of Process-Independent Class-AB Single-Stage OTAs for Low-Power SC Circuits

Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

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