Constrained Parity-Check Code and Post-Processor for Advanced Blue Laser Disc Systems

Abstract

We propose an advanced detection approach based on capacity-approaching constrained parity-check codes and multiple-error-event correction post-processing for high-density blue laser disc systems. Simulation results for an idealized blue laser disc system show that at high recording density, a performance improvement of 1.7 dB is achieved over the standard 17PP code without parity.

Error Correction Code Failure Rate Analysis for Parity-Check-Coded Optical Recording Systems

“…This is another indication that the BER for the 4-bit PC code is smaller than that of the rate 9/13 code. 7) However, the probabilities of long byte errors (i.e., larger than 3 byte errors) are higher for cases with PC. These long byte errors are mainly caused by the mis-corrections of the post-processors.…”

“…For the case with PC, we use a rate 277/406 d ¼ 1 constrained 4-bit PC code in conjunction with a double-error-event correction post-processor. 7) The 4-bit constrained PC code can detect all the dominant error events at the output of the Viterbi detector with the code rate approaching the capacity. 7) The Fourier transform of the channel symbol response h k is expressed as 15) HðÞ ¼…”

“…7) The 4-bit constrained PC code can detect all the dominant error events at the output of the Viterbi detector with the code rate approaching the capacity. 7) The Fourier transform of the channel symbol response h k is expressed as 15) HðÞ ¼…”

“…3,6) Furthermore, the combination of Reed-Solomon (RS) outer codes and paritycheck (PC) inner codes in conjunction with post-processing is projected to be highly promising for the next (4th) generation optical recording systems. 7) In recent years, there have been several papers on post-ECC analysis of the PC-code-based detection approaches for magnetic recording systems. In refs.…”

A general construction of constrained parity-check codes for optical recording

“…The dominant error events at the Viterbi detector output turn out to be ±{2, 0, −2}, ±{2}, ±{2, 0, −2, 0, 2}, ±{2, 0, −2, 0, 2, 0, −2}, and ±{2, 0, 0, −2}. At the output of the Viterbi detector, a matched-filtering type post-processor is used, which can correct both single and double error events that occur within each detected codeword [21]. The postprocessor is essentially a soft-decision decoder of the PC code, and it is widely accepted in practice due to its simplicity [10], [12].…”