Constrained-random bitstream generation for H.264/AVC decoder conformance test

Efficient test bitstream generation method for verification of HEVC decoders

“…The number of low-level SEs, which are in the slice data (SD), is relatively small while they appear much more frequently in the bitstreams. To substantially reduce spatial and temporal correlation among the pixels, their values are selected using the constrained-random (CR) generation method [3] instead of using the pixels values in the natural image sequence.…”

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

“…code or gate-level netlist, a Universal Verification Methodology (UVM) [16,18] ver- such as timing check by assertions [76], a reusable framework to obtain functional and code coverage [82], and constrained random data generation [85], we also utilize several bus performance models (BPM) in this test bench to examine the bus performance in real time. The models are coded by System Verilog language, and are reusable, configurable, and seamlessly compatible with the UVM methodology.…”

“…[103,69], assertion-based verification [76,34], and constraint-random verification [85], can be certainly reused in the IoT chip design. Moreover, the cost of verification has been rising faster than design and it has been identified as one of the areas in which new solutions may be appropriate for the types of design seen on the edge of the IoT.…”

“…System Verilog Language [13], thus it can be seamlessly integrated into the UVM test bench, and compatible with the traditional verification methods, such as assertion-based verification [76,34], coverage-driven verification [82], and the constrained random test [85].…”

“…In our work, we set up the verification environment using the UVM methodology [16,18], employing traditional verification methods, such as assertion verification [76], [82] and the constrained random test [85]. …”