Constructive Boolean circuits and the exactness of timed ternary simulation

Abstract

We classify gate level circuits with cycles based on their stabilization behavior. We define a formal class of combinational circuits, the constructive circuits, for which signals settle to a unique value in bounded time, for any input, under a simple conservative delay model, called the up-bounded non-inertial (UN) delay. Since circuits with combinational cycles can exhibit asynchronous behavior, such as non-determinism or metastability, it is crucial to ground their analysis in a formal delay model, which previous work in this area did not do.We prove that ternary simulation, such as the practical algorithm proposed by Malik, decides the class of constructive circuits. We prove that three-valued algebra is able to maintain correct and exact stabilization information under the UN-delay model, and thus provides an adequate electrical interpretation of Malik's algorithm, which has been missing in the literature. Previous work on combinational circuits used the upbounded inertial (UI) delay to justify ternary simulation. We show that the match is not exact and that stabilization under the UI-model, in general, cannot be decided by ternary simulation. We argue for the superiority of the UN-model for reasons of complexity, compositionality and electrical adequacy. The UN-model, in contrast to the UI-model, is consistent with the hypothesis that physical mechanisms cannot implement non-deterministic choice in bounded time.As the corner-stone of our main results we introduce UN-Logic, an axiomatic specification language for UN-delay circuits that mediates between the real-time behavior and its abstract simulation in the ternary domain. We present a symbolic simulation calculus for M. Mendler ( ) Faculty 284 Form Methods Syst Des (2012) 40:283-329 circuit theories expressed in UN-logic and prove it sound and complete for the UN-model. This provides, for the first time, a correctness and exactness result for the timing analysis of cyclic circuits. Our algorithm is a timed extension of Malik's pure ternary algorithm and closely related to the timed algorithm proposed by Riedel and Bruck, which however was not formally linked with real-time execution models.

Denotational fixed-point semantics for constructive scheduling of synchronous concurrency

“…The ideal is a situation like in [64] where it is shown that Berry's must-cannot analysis [12] when applied to circuits is (sound and) complete for scheduling under non-inertial delays. In another direction, it will be interesting to search for suitable, more expressive, extensions of the domain I (D, P) in which the fixed-point analysis of pSCL is complete for SC-constructiveness as defined in [86].…”

“…2 The only available result on the lower-level operational soundness of the fixed-point construction is indirect, has never formally been proven and applies to the hardware translation given in [12]. At the hardware level it is known that constructiveness implies delay-insensitivity under non-inertial delays [58,64,76]. While this highlights the universal nature of the constructive semantics, it does not provide insights into the nature of constructiveness for software implementations of SMoCC languages.…”

“…Observe that the well-known ternary domain (Kleene) for the fixed-point analysis of Pure Esterel [12] or constructive Boolean circuits [64] is captured, as indicated in Fig. 3, by the inner part with values [0, 0] ("absent"), [1,1] ("present") and [0, 1] ("undefined").…”

“…Causal Esterel programs on pure signals satisfy a strong scheduling invariant: they can be translated into constructive circuits which are delay-insensitive [18] under the non-inertial delay model, which can be fully decided using ternary Kleene algebra [64]. This makes Malik's work [58] on causality analysis of cyclic circuits applicable to constructiveness analysis of (instantaneous) Esterel program.…”

Synchronous digital circuits as functional programs

“…Shiple et al [1996] have grounded this parallel semantics in the physical models of Brzozowski and Seger [1995]. The connection with constructive logic continues to be explored by Mendler et al [2012], and Riedel and Bruck [2003] show that cycles can yield significant space reductions in practice.…”