Contactless Testing of Circuit Interconnects

Abstract

State-of-the-art printed circuit boards (PCBs) have become extremely dense and are not fully accessible for applying physical testing solutions. Extra steps are required in the design and manufacturing process for testing advanced printed wiring boards (PWBs) with embedded passive components. This processing is further complicated by upcoming sequential build-up (SBU) technologies that provide feature sizes smaller than 10 μm and that do not allow physical access for testing the interconnect between two pads. In this paper, we propose a new contactless technique for overcoming the SBU challenge for testing interconnects between embedded components. A test trace is employed as a sensor, which senses the terminations of the trace being tested. The simulation and analysis results of this study demonstrate the feasibility of this concept for application to SBU and conventional PCB/PWB interconnect testing to overcome the barriers to physical access. Robustness of the approach has been studied against packaging deviations and possible testing process variations. To ensure defect detection with feasible margins, design for testability (DfT) rules have been established for practical PCB dimensions.

Application of Contactless Testing to PCBs with BGAs and Open Sockets

“…This voltage ratio is dependent on the load capacitance of I C 1 and I C 2 as discussed in the previous work [11]. Depending on the required quality, this solution can be applied to: Contactless PCB testing which is based on broadsidecoupled stripline structure relies on the pre-known IO capacitances of the connected ICs [11]. The transmission parameter S21, which is measured between the ports of the test trace in the upper part of the structure, carries informa- tion about the terminations of the trace in the UUT which is the lower part of the structure.…”

“…This voltage ratio is dependent on the load capacitance of I C 1 and I C 2 as discussed in the previous work [11]. Depending on the required quality, this solution can be applied to: Contactless PCB testing which is based on broadsidecoupled stripline structure relies on the pre-known IO capacitances of the connected ICs [11].…”

“…In some cases, the silicon manufacturers may not provide the IO capacitances in their data sheets, simply because the IO capacitances are less important within the operating frequency from signal integrity point of views and thus limitations to simulating the first resonance frequencies for preparing test data. To keep the contactless testing approach applicable in such situations, this paper introduces the combination of the standard score statistical measurement with the contactless test approach [11]. Experiments in conventional PCBs with BGA packages and open sockets show the effectiveness of the method in detecting possible opens and bridges.…”

“…On the other hand, the AXI solution is expensive and slow for testing every manufactured PCB, especially for electronics where long-term reliability is not important. Moreover, boundary-scan testing which has seen great progress from standardization point of view is not always applicable, this is due to diversity of today PCBs which may contain non-boundary-scan-compliant components [4,11].…”

“…To improve the flexibility of today's test strategy and test PCB interconnects when it is not possible with today's solutions, a novel approach for testing conventional PCBs has been proposed in [11], based on broadside-coupled stripline structure where hidden interconnects are testable in a passive Unit Under Test (UUT are closed, the sensing line and the line under test form a broadside-coupled stripline structure with high coupling through a small thickness of the solder mask layers. The voltage ratio…”