Contention-avoiding custom topology generation for network-on-chip

Deniziak, Stanislaw; Tomaszewski, Robert

doi:10.1109/ddecs.2009.5012136

Cited by 9 publications

(2 citation statements)

References 12 publications

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“…It also does not directly address power dissipation due to the probes. Deniziak et al suggest rescheduling tasks and performing link insertion within the network to avoid contention [31]. The method only considers mesh topologies and does not directly deal with the power consumption of extra routers and links.…”

Section: Performance Degradation In Noc Designmentioning

confidence: 99%

Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures

Tino¹

2021

Preprint

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Network-on-Chip (NoC) communication interconnects have emerged as a solution to complex heterogeneous core systems such as those found in Multiprocessor System-on-Chip architectures. Many previous works have used the objectives of power or performance during topology synthesis for regular or application specific based NoC design. However, given the crucial requirements and demands of future on-chip applications, it is imperative that designs consider both power and performance aspects, in addition to other important system constraints. Therefore, in order to address such issues, this thesis work presents a multi-objective Tabu search based topology synthesis technique for designing power and performance efficient Network-on-Chip architectures. The methodology incorporates an analytical and simulation approach in order to compromise between computational time and effort within the algorithm. Furthermore, this work also presents a novel approach for a power and performance tradeoff during contention and deadlock removal within synthesis. The proposed method was tested using seven different multimedia and network benchmark application, where results displayed an increase in performance and decrease in power dissipation in comparison to other previous application specific and regular mesh designs. The analysis method was successful during topology generation, yielding an overall accuracy rate deviation of 19.8% within the worst case scenario.

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Section: Performance Degradation In Noc Designmentioning

confidence: 99%

Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures

Tino¹

2021

Preprint

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“…하지만 현재 표준화된 NoC 프로토콜의 부재 및 기존 버스 프로토콜로 설계되어진 legacy IP의 호환성 문제 [2] (548) 적용한 토폴로지 합성 방법 [3] , 링크 추가를 통한 대체 경로 생성 방법, 메시지 스케줄링을 적용하여 지연시간 을 개선하는 방법 [4] 크를 제안하였고 [6] , Mishra et al은 대역폭과 지연시간 각각에 최적화된 분리 네트워크를 사용하는 NoC 설계 방식을 제안하였다 [7] . 또한 A.…”

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Separated Address/Data Network Design for Bus Protocol compatible Network-on-Chip

정승아¹,

이재훈²,

김상헌³

et al. 2016

Journal of the Institute of Electronics and Information Enginee

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As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

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