Continuous-Time Common-Mode Feedback Circuit for Applications with Large Output Swing and High Output Impedance

Yan, Weixun; Zimmermann, Horst

doi:10.1109/ddecs.2008.4538757

Cited by 12 publications

(7 citation statements)

References 8 publications

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“…As practical example, the CMFB loop of a fully-differential (FD) two-stage Miller-compensated operational transconductance amplifier (OTA), is affected by several parasitic poles. Since the dominant pole is set by the Miller compensation that is designed to satisfy specifications on the differential signal, these poles degrade the phase margin of the CMFB, thus making very difficult to have an unity-gain frequency comparable with that of the differential amplifier [30]. Moreover, the external feedback loop results in a positive reaction for what concerns the common-mode signal, so that to avoid instability a careful design is required [31].…”

Section: Introductionmentioning

confidence: 98%

“…Several CMFB configurations have been presented in the literature [27][28][29][30][31][32], using both continuous-time (CT) and switched-capacitor (SC) topologies. A detailed description of major features of these techniques can be found in [27,28].…”

Section: Introductionmentioning

confidence: 99%

“…This topology offers the best performance in terms of loop gain, bandwidth and linearity, but the sensing resistors should be very large to guarantee the gain of the system is not deteriorated. However, large resistors lead to huge noise and parasitic effects as also a gate leakage at input of the error amplifier (usually with a capacitive type impedance), especially in nanoscale technologies [30].…”

Section: Introductionmentioning

confidence: 99%

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An improved common-mode feedback loop for the differential-difference amplifier

Centurelli

Simonetti

Trifiletti

2012

Analog Integr Circ Sig Process

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Unconditional stability of the high-gain amplifiers is a mandatory requirement for a reliable steady-state condition of time-discrete systems, especially for all blocks designed to sample-and-hold (S/H) circuits. Compared to differential path, the common-mode feedback loop is often affected by poles and zeros shifting that degrades the large signal response of the amplifiers. This drawback is made worse in some well-known topologies as the difference-differential amplifier (DDA) that shows non-constant transconductance and poor linearity. This work proposes a body-driven positive-feedback frequency compensation technique (BD-PFFC) to improve the linearity for precision DDA-based S/H applications. Theoretical calculations and circuit simulations carried out in a 0.13 mu m process are also given to demonstrate its validity

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Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An improved common-mode feedback loop for the differential-difference amplifier

Centurelli

Simonetti

Trifiletti

2012

Analog Integr Circ Sig Process

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“…In this work, a CT CMFB circuit which combines high input impedance and rail-to-rail output swing is utilized. Figure 5-2 shows the CMFB circuit which has been adopted from [97]. Since all the nodes in Figure 5-2 except the output node vCmfb2 are low-impedance nodes, the CMFB circuit does not create low-frequency poles which can degrade the stability of the OTA.…”

Section: Common-mode Feedbackmentioning

confidence: 99%

“…Since a switched-capacitor (SC) CMFB limits the maximum input signal frequency and requires generation of non-overlapped clocks, a continuous-time (CT) CMFB has been employed in the second stage. Figure 5-10 shows the CT CMFB adopted from [97] along with FBB voltages. The use of complementary source-followers to detect the output CM level enables rail-to-rail output swing without loading the OTA outputs.…”

Section: Ota Architecturementioning

confidence: 99%

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At V DD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm 2 .The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-tohigh sampling rates, the DAC reference settling poses a speed bottleneck in chargeredistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well iv critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the ...

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Circuits and Systems for Multi-Channel Neural Recording

Bafar

Schmid

2013

Wireless Cortical Implantable Systems

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Continuous-Time Common-Mode Feedback Circuit for Applications with Large Output Swing and High Output Impedance

Cited by 12 publications

References 8 publications

An improved common-mode feedback loop for the differential-difference amplifier

An improved common-mode feedback loop for the differential-difference amplifier

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Circuits and Systems for Multi-Channel Neural Recording

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