Continuous Time Sigma-Delta Modulator with VCO-based integrators and optimized NTF zeros

Medina, Víctor Manuel Pina; Alvero-Gonzalez, Leidy Mabel; Gutierrez, Eric; Patón, S.; Hernández, Luis

doi:10.1109/icecs46596.2019.8964936

Cited by 2 publications

(2 citation statements)

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“…The maximum frequency for the PC output pc out and the considered input range is not higher than 100 MHz. The phases selected for the PC must be equidistant such that the frequency at the output of the phase combiner is effectively increased and so does the SQNR [36].…”

Section: A First Integrator Stagementioning

confidence: 99%

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A maximally-digital VCO-ADC with inherent mixing input capability

Medina

Garvi

Gutierrez

et al. 2022

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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One of the limitations of conventional VCO-ADCs is the restriction to first-order noise shaping. True-VCO architectures have been proposed to increase the noise-shaping order by cascading several VCO integrators, but without requiring analog feedback loops. A high noise-shaping order allows to reduce the input VCO frequency compared to a conventional VCO-ADC with similar dynamic range, which improves power consumption. Prior-art True-VCO architectures represent state variables either with a thermometer code or with a single-bit. Thermometer encoding is a natural choice when ring oscillators are selected as loop filter integrators. However, chip area restrictions force thermometer-encoded state variables to have few levels. A reduced number of levels in the state variables limits the dynamic range of True VCO-ADCs. In this paper, we show experimentally a second-order audio VCO-based ADC which uses ring oscillators as integrators but employs Gray and binary encoding for state variables. As a consequence, the complexity and area of the True-VCO architecture is reduced, breaking the barrier that limits the dynamic range of prior designs. The implemented chip shows a dynamic range of 103 dB achieving a peak SNDR of 76.5 dB-A with a power of 250 µW occupying 0.095 mm 2 in 130 nm CMOS.

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Section: A First Integrator Stagementioning

confidence: 99%

“…However, single inverter ROs must have an odd number of phases. Unevenly distributed phases degrade the SQNR, as described in [36], and therefore we have preferred the differential RO.…”

Section: A First Integrator Stagementioning

confidence: 99%