Control of dipole properties in high-k and SiO2 stacks on Si substrates with tricolor superstructure

Abstract

The concept of the tricolor superstructure (TCS), which is a triple-layer stack structure containing two types of high dielectric constant (high-k) layers (designated HK1 and HK2) and a SiO2 layer, is proposed to control the moment and the polarity of the interface dipole layer that are induced at the high-k/SiO2 interfaces. The interface dipole layer is formed by oxygen ion migration from the layer with higher oxygen areal density (σ) to that with lower σ. When the two high-k materials are selected with the order of σHK1 > σSiO2 > σHK2 in a SiO2/HK2/HK1/SiO2 TCS, the dipole directions of the interface dipole layers at the SiO2/HK2 and the HK1/SiO2 interfaces are aligned. Additionally, in the transposed SiO2/HK1/HK2/SiO2 TCS, the total polarity is reversed. The concept is demonstrated using Al2O3 and Y2O3 layers because they offer the order of σAl2O3 > σSiO2 > σY2O3. The two stacking sequence samples composed of SiO2/Y2O3/Al2O3/SiO2 and SiO2/Al2O3/Y2O3/SiO2 that were fabricated using superlattice technique by pulsed laser deposition obviously show opposite dipole polarities. Increasing repetition of the deposited TCS unit also causes the dipole moments to increase systematically. The TCS technique enables control of the properties of the interface dipole layer at high-k/SiO2 interfaces in amorphous systems.

How flat is the flatband potential?

“…2a and 3c). Also, the addition of an alumina layer on top of the Si/SiO 2 interface could generate a dipole 69–71 which compensates partially the surface potential drop induced by the defects at the Si/SiO 2 interface. Thus, the Si/SiO 2 /Al 2 O 3 structure would be more favorable, under certain conditions of fabrication, to the build-up of a SCR in the silicon if Pt is deposited on top.…”

Diode-Like Current Leakage and Ferroelectric Switching in Silicon SIS Structures with Hafnia-Alumina Nanolaminates

“…Their removal was controlled by C-V and pseudo-MOSFET measurements at different sweeping rates (see e.g., Figure 1 , Figure 4 and Figure 8 ). To minimize the leakage currents through the SIS structure, a 20-nm-thick alumina layer was firstly investigated as an insulator after different thermal treatments due to its high bandgap and amorphous phase stability [ 26 , 27 , 28 ].…”

“…An increase in the thickness of aluminum oxide layer inserts by a factor of 5 reduces the leakage current by 4 orders of magnitude. However, in the case of Al 2 O 3 contact with the silicon interface, the problem of built-in positive charge in the insulator arises again and, possibly, that of the formation of dipoles at Al 2 O 3 or HfO 2 heterointerfaces with SiO 2 interlayers [ 28 , 29 ].…”

“… ( a ) Linear approximations of normalized differential conductance (NDC, according to [ 28 ], for the leakage current at the drain–gate contacts in the “forward” direction shown in the coordinates of 1/V for a larger bias voltage based on the data extracted from Figure S2 ; ( b ) the same in the V 1/2 coordinates for a lower value of bias voltage. …”

“…Their removal was controlled by C-V and pseudo-MOSFET measurements at different sweeping rates (see e.g., Figures 1, 4 and 8). To minimize the leakage currents through the SIS structure, a 20-nm-thick alumina layer was firstly investigated as an insulator after different thermal treatments due to its high bandgap and amorphous phase stability [26][27][28]. Figure 2a shows the hysteresis-like drain-gate characteristics of n-SIS pseudo-MOSFETs with a 500 nm n-Si layer and a 20 nm insulator layer of an ALD Al 2 O 3 layer immediately after the furnace annealing at 450 • C for the sweep range of V g = −1.0 + 0.5 Volts.…”