Control of limit cycles in buck converters

Condon, Marissa; Hayes, Brendan

doi:10.1108/compel-09-2013-0293

Cited by 2 publications

(2 citation statements)

References 12 publications

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“…The presence of the saturation block within the loop (Figure 5) can provide additional compression of the signal at the oscillation frequency. In the case of sinusoidal-type limit cycle oscillation, describing function method may be used for the non-linear saturation occurring in the loop (Condon and Hayes, 2014). The describing function (Franklin et al , 2015) of a gain stage with saturation for an input signal of amplitude A is given by equation (14): …”

Section: Stability and Non-linear Behaviourmentioning

confidence: 99%

Analysis of feedback predictive encoder based ADCs

Scanlan

O’Hare

Halton

et al. 2017

COMPEL

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ABSTRACT:Purpose-The purpose of this paper is to present analysis of the feedback predictive encoder based ADC (Analog-to-Digital Converter).Design/methodology/approach-The use of feedback predictive encoder based ADCs presents an alternative to the traditional two stage pipeline ADC by replacing the input estimate producing first stage of the pipeline, with a predictive loop that also produces an estimate of the input signal. Findings-The overload condition for feedback predictive encoder ADCs is dependent oninput signal amplitude and frequency, system gain and filter order. The limitation on the practical useable filter order is set by limit cycle oscillation. A boundary condition is defined for determination of maximum useable filter order. In a practical implementation of the predictive encoder ADC, the time allocated to the key functions of the gain stage and loop quantizer leads to optimisation of the power consumption.Originality/value-This paper presents a methodology to optimise the bandwidth of predictive encoder ADCs. The overload and stability conditions may be used to determine the maximum input signal bandwidth for a given loop quantizer. Optimisation of power consumption based on the allocation of time between the gain stage and the SAR ADC operation is investigated.The lower bound of power consumption for this architecture is estimated. Paper Type-Research Paper

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Section: Stability and Non-linear Behaviourmentioning

confidence: 99%

Analysis of feedback predictive encoder based ADCs

Scanlan

O’Hare

Halton

et al. 2017

COMPEL

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“…As DSP-based digital control is becoming more common in several industries, apposite factors are needed to be considered while designing and implementing a digital control loop for SMPS. Several pertinent factors such as sampling, quantization and steady state limit cycle oscillation error (Condon and Hayes, 2014) due to low resolution of ADC and digital pulse width modulation (Gao et al, 2008), dead time optimization (Peterchev and Sanders, 2006), delays in close loop control needs to be addressed. An experimental study has also been done (Muppala Kumar et al, 2018) to show the behaviour of voltage-mode controlled converter, when the reference voltage is coupled with different frequency.…”

Section: Introductionmentioning

confidence: 99%

A comparative study of phase margin based digital and analog controlled synchronous buck with optimum LC filter

Rashmi

Jagtap

2019

COMPEL

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Purpose Traditionally, industrial power supplies have been exclusively controlled through analog control to sustain high reliability with low cost. However, with the perpetual decrement in cost of digital controllers, the feasibility of a digitally controlled switch mode power supply has elevated significantly. This paper aims to outline the challenges related to the design of digital proportional-integral (PI) controlled synchronous rectifier (SR) buck converter by comparing controller performance in continuous and discrete time. The trapezoidal approximation-based digital PI control is designed for low voltage and high-frequency SR buck converter operating under continuous conduction mode. Design/methodology/approach The analog and digital controller are designed using a SISO tool of MATLAB. Here, zero-order hold transform is used to convert the transfer function from continuous to discrete time. Frequency and time domain analysis of continuous plant, discrete plant and close loop system is performed. The designed digital PI control is simulated in MATLAB Simulink. The simulated results is also verified on hardware designed around digital signal processing control. Findings The continuous and discrete control loops are validated with multiple tests in the time and frequency domain. The detailed steady state theoretical analysis and performance of the SR buck converter is presented and verified by simulation. It is found that the delay in digital control loop results in a low phase margin. This phase margin decreases with higher bandwidth. The hardware experiments with the digital control loop are carried out on a 10 W prototype. The chosen parameters for the SR buck converter are found to be optimum for steady and transient state response. Originality/value This paper compares the digital and analog control approach of compensator design. It focuses on the implications created at the time of transforming the control design from continuous to discrete time. Further, it also focuses on the selection of parameters such as phase margin, bandwidth and low pass filter.

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Control of limit cycles in buck converters

Cited by 2 publications

References 12 publications

Analysis of feedback predictive encoder based ADCs

Analysis of feedback predictive encoder based ADCs

A comparative study of phase margin based digital and analog controlled synchronous buck with optimum LC filter

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