The persistent advancement of miniaturized electronic devices and their increased performance exacerbates the challenges concerning efficient heat transfer. This study explores innovative configurations of parallel plate-fin heat sink for MOSFET cooling, combining experimental validation and numerical simulations using the ANSYS Fluent solver. A heat sink, denoted as HS1, featuring seven parallel plate fins of length <i>L</i>, serves as the subject of both experimental and numerical analysis. Five alternative configurations designated HS2 to HS6 maintain the overall length of HS1 whilst examining different segmentations of the middle fins. HS2, HS3, and HS4 are segmented with lengths <i>L</i>/3, <i>L</i>/4, and <i>L</i>/7, respectively. Introducing staggered fins, HS5 and HS6, segmented with <i>L</i>/7, generates translations of <i>L</i>/14 and <i>L</i>/28, respectively. Staggered fins are positioned across all proposed heat sinks at <i>S</i>/2 (<i>S</i> is the fins spacing). Analysis of combined mass flow rate and power losses on HS1 reveals distinct trends in thermal resistance and maximum junction temperatures with varying mass flow rates. The heat sink configurations exhibit a significant reduction in thermal resistance compared to HS1. The exploration of the thermo-fluidic characteristics of each configuration unveils the intricate fluid dynamics and heat transfer phenomena occurring within the heat sinks. These configurations aim to minimize the thermal resistance between the MOSFETs' junction and the ambient, effectively reducing operational temperatures. Results also demonstrate significant improvements in heat dissipation efficiency, with the best configuration showcasing a reduction in thermal resistance up to 25.37%.