Conversion of control dependence to data dependence

Allen, John R.; Kennedy, Ken; Porterfield, Carrie; Warren, Joe

doi:10.1145/567067.567085

Cited by 476 publications

(259 citation statements)

References 5 publications

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“…In this step, a Guard Condition [23] for each basic block is computed. A Guard Condition is a boolean expression which specifies if the instructions of the corresponding basic block have to be executed or not.…”

Section: Guard Conditions Computationmentioning

confidence: 99%

“…A Guard Condition is a boolean expression which specifies if the instructions of the corresponding basic block have to be executed or not. Differently from [23] and [5] the predicates are not exploited to completely remove control constructs from the parallel loop. These expression will indeed be used in the following steps as operand of predicated instructions and to correctly manage reaching definitions.…”

Section: Guard Conditions Computationmentioning

confidence: 99%

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Exploiting vectorization in high level synthesis of nested irregular loops

Lattuada

Ferrandi

2017

Journal of Systems Architecture

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Synthesis of DoAll loops is a key aspect of High Level Synthesis since they allow to easily exploit the potential parallelism provided by programmable devices. This type of parallelism can be implemented in several ways: by duplicating the implementation of body loop, by exploiting loop pipelining or by applying vectorization.In this paper a methodology for the synthesis of nested irregular DoAll loops based on outer vectorization is proposed. The methodology transforms the intermediate representation of the DoAll loop to introduce vectorization and it can be easily integrated in existing state of the art High Level Synthesis flows since does not require any modification in the rest of the flow. Vectorization is not limited to perfectly nested countable loops: conditional constructs and loops with variable number of iterations are supported. Experimental results on parallel benchmarks show that the generated parallel accelerators have significant speed-up with limited penalties in terms of resource usage and frequency decrement.

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Section: Guard Conditions Computationmentioning

confidence: 99%

Section: Guard Conditions Computationmentioning

confidence: 99%

Exploiting vectorization in high level synthesis of nested irregular loops

Lattuada

Ferrandi

2017

Journal of Systems Architecture

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“…To use SIMD instructions in the presence of diverging control flow, the programmer or the compiler has to replace control flow by data flow [2]. For code without loops, this is commonly called if conversion.…”

Section: Introductionmentioning

confidence: 99%

Whole-function vectorization

Karrenberg

Hack

2011

International Symposium on Code Generation and Optimization (CGO 2011)

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Abstract-Data-parallel programming languages are an important component in today's parallel computing landscape. Among those are domain-specific languages like shading languages in graphics (HLSL, GLSL, RenderMan, etc.) and "general-purpose" languages like CUDA or OpenCL. Current implementations of those languages on CPUs solely rely on multi-threading to implement parallelism and ignore the additional intra-core parallelism provided by the SIMD instruction set of those processors (like Intel's SSE and the upcoming AVX or Larrabee instruction sets).In this paper, we discuss several aspects of implementing dataparallel languages on machines with SIMD instruction sets. Our main contribution is a language-and platform-independent code transformation that performs whole-function vectorization on low-level intermediate code given by a control flow graph in SSA form.We evaluate our technique in two scenarios: First, incorporated in a compiler for a domain-specific language used in realtime ray tracing. Second, in a stand-alone OpenCL driver. We observe average speedup factors of 3.9 for the ray tracer and factors between 0.6 and 5.2 for different OpenCL kernels.

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“…The values of predicates are manipulated by a set of predicate defining instructions. To explore predication, the compiler generally uses a technique called if-conversion [1], which eliminates branch instructions and replaces affected instructions with predicate defining instructions and predicated forms. This technique enlarges the scope of instruction scheduling and avoids branch misprediction penalties that may be caused by the eliminated branches.…”

Section: Introductionmentioning

confidence: 99%

“…Suppose the compiler applies ifconversion [1] to eliminate the branchs in block 2. This leads to Figure 1(b), where the blocks 2 -5 have been merged into a new hyperblock HB.…”

Section: Introductionmentioning

confidence: 99%

Region-Based Partial Dead Code Elimination on Predicated Code

Cai

Gao

Xue

2004

Lecture Notes in Computer Science

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Abstract. This paper presents the design, implementation and experimental evaluation of a practical region-based partial dead code elimination (PDE) algorithm on predicated code in an existing compiler framework. Our algorithm processes PDE candidates using a worklist and reasons about their partial deadness using predicate partition graphs. It operates uniformly on hyperblocks and regions comprising basic blocks and hyperblocks. The result of applying our algorithm to an SEME region is optimal: partially dead code cannot be removed without changing the branching structure of the program or potentially introducing new predicate defining instructions. We present statistic evidence about the PDE opportunities in the 12 SPECint2000 benchmarks. In addition to exhibit small compilation overheads, our algorithm achieves moderate performance improvements in 8 out of the 12 benchmarks on an Itanium machine. Our performance results and statistics show the usefulness of our algorithm as a pass applied before instruction scheduling.

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Conversion of control dependence to data dependence

Cited by 476 publications

References 5 publications

Exploiting vectorization in high level synthesis of nested irregular loops

Exploiting vectorization in high level synthesis of nested irregular loops

Whole-function vectorization

Region-Based Partial Dead Code Elimination on Predicated Code

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