Converter Utilization Ratio Enhancement in the THD Optimization of Cascaded H-Bridge 7-level Inverters

Abstract

In this paper, a new technique for harmonic optimization in cascaded H-bridge 7-level inverters is proposed. The suggested strategy is based on minimizing an objective function which simultaneously optimizes the converter utilization and Total Harmonic Distortion (THD). The Switch Utilization Ratio (SUR) is formulized for both the phase and line-line voltages of a 7-level inverter and is considered in the final objective functions. Based upon the SUR formula, utilization ratio enhancement will reduce the value of feeding DC links, which improves the efficiency and lifetime of the circuit components due to lower voltage stresses and losses. In order to achieve more effective solution in different modulation indices, it is assumed that the DC sources can be altered. Experimental validation is presented based on a three-phase 7-level inverter prototype.

Switching Angles Calculation in Multilevel Inverters Using Triangular Number Sequence –A THD Minimization Approach

“…An alternative is to calculate the switching angles in such a manner that the overall THD is minimized [11]. In comparison with other modulation methods, this approach provides an acceptable performance with low switching frequency to fundamental frequency ratios.…”

Asymmetrical Cascade Multilevel Inverter Design using Modified Level Shift Pulse Width Modulation

“…The multi-level inverter (MLI)topology use small amount of voltage magnitude to get the require voltage magnitude [1]. In recent years,the advantage of MLI for instance high power quality, low voltage stress devices, also lesser switching loss cause them to be topic of on-going studies [2] furthermore, the application of inverter in high voltage directcurrent (DC) [3].To get better inverter performance and output quality, various methods are suggested, which include Sinusoidal Pulse Width Modulation (SPWM), Space-Vector Modulation (SVM) [4], optimal minimization of THD [5]. Several topologies,configurations have suggested for MLIs.…”