Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming

Cheng, Huimei; Li, Xi; Gu, Yichen; Beerel, Peter A.

doi:10.1109/tcad.2021.3068109

Cited by 4 publications

(11 citation statements)

References 27 publications

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“…Fojtik et al [1] analyze a two clock-phase latch-based implementation of Razor flops to detect errors in an ARM Cortex-M3 processor. Cheng et al [17] discuss a conversion algorithm using three clock phases to improve area and power consumption. Yoshikawa et al [18] present a singlephase forward retiming algorithm for FF-based design conversion, using commercial tools for retiming.…”

Section: Single and Multi-phase Clock Solutionsmentioning

confidence: 99%

Section: Comparison With Other Workmentioning

confidence: 99%

“…Some of our results can be directly compared with those presented in [17], which converts an FF-based netlist to a 3phase PTL-based netlist using two variants of the same algorithm. While our main goal is to improve the maximum operating frequency, [17] focuses instead on reducing the area occupation. For this reason, despite the differences in technol- ogy and implementation setup, the area overhead introduced by our optimization algorithm is compared with the results of [17].…”

Section: Comparison With Other Workmentioning

confidence: 99%

“…While our main goal is to improve the maximum operating frequency, [17] focuses instead on reducing the area occupation. For this reason, despite the differences in technol- ogy and implementation setup, the area overhead introduced by our optimization algorithm is compared with the results of [17]. There are six common benchmark circuits used by us and [17], four from CEP and two from ISCAS89.…”

Section: Comparison With Other Workmentioning

confidence: 99%

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Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

et al. 2023

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Flip-flops are the most used sequential elements in synchronous circuits, but designs based on latches can operate at higher frequencies and occupy less area. Techniques to increase the maximum operating frequency of flip-flop based designs, such as time-borrowing, rely on tight hold constraints that are difficult to satisfy using traditional back-end optimization techniques. We propose Mix & Latch, a methodology to increase the operating frequency of synchronous digital circuits using a single clock tree and a mixed distribution of positive-and negative-edge-triggered flops, and positive-and negative-levelsensitive latches. An efficient mathematical model is proposed to optimize the type and location of the sequential elements of the circuit. We ensure that the initial registers are not moved from their initial location, although they may change type, thus allowing the use of equivalence checking and static timing analysis to verify formally the correctness of the transformation. The technique is validated using a 28 nm CMOS FDSOI technology, obtaining 1.33 X post-layout average operating frequency improvement on a broad set of benchmarks over a standard commercial design flow. Additionally, the circuit area was also reduced by more than 1.19 X on average for the same benchmarks, although the overall area reduction is not a goal of the optimization algorithm. To the best of our knowledge, this is the first work that proposes combining mixed-polarity flip-flops and latches to improve the circuit performance.

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Section: Single and Multi-phase Clock Solutionsmentioning

confidence: 99%

Section: Comparison With Other Workmentioning

confidence: 99%

Section: Comparison With Other Workmentioning

confidence: 99%

Section: Comparison With Other Workmentioning

confidence: 99%

See 2 more Smart Citations

Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

et al. 2023

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“…The second method to improve circuit performance in the traditional paradigm is retiming, which moves sequential components, e.g., flip-flops, but still preserves the correct functional behavior of circuits. The existing retiming methods usually focus on reducing execution time while improving the performance of digital circuits [12]- [16]. Useful clock skew is the third method to enhance timing performance of digital circuits.…”

Section: Metmentioning

confidence: 99%

VirtualSync+: Timing Optimization with Virtual Synchronization

Zhang¹,

Li²,

Huang³

et al. 2022

Preprint

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In digital circuit designs, sequential components such as flip-flops are used to synchronize signal propagations. Logic computations are aligned at and thus isolated by flip-flop stages. Although this fully synchronous style can reduce design efforts significantly, it may affect circuit performance negatively, because sequential components can only introduce delays into signal propagations but never accelerate them. In this paper, we propose a new timing model, VirtualSync+, in which signals, specially those along critical paths, are allowed to propagate through several sequential stages without flip-flops. Timing constraints are still satisfied at the boundary of the optimized circuit to maintain a consistent interface with existing designs. By removing clock-to-q delays and setup time requirements of flip-flops on critical paths, the performance of a circuit can be pushed even beyond the limit of traditional sequential designs. In addition, we further enhance the optimization with VirtualSync+ by finetuning with commercial design tools, e.g., Design Compiler from Synopsys, to achieve more accurate result. Experimental results demonstrate that circuit performance can be improved by up to 4% (average 1.5%) compared with that after extreme retiming and sizing, while the increase of area is still negligible. This timing performance is enhanced beyond the limit of traditional sequential designs. It also demonstrates that compared with those after retiming and sizing, the circuits with VirtualSync+ can achieve better timing performance under the same area cost or smaller area cost under the same clock period, respectively.

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Blade-DA: Click-Based Asynchronous Resilient Circuit With Dynamic Delay Adjustment

Zhang,

Xiong,

Zhang

et al. 2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming

Cited by 4 publications

References 27 publications

Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

VirtualSync+: Timing Optimization with Virtual Synchronization

Blade-DA: Click-Based Asynchronous Resilient Circuit With Dynamic Delay Adjustment

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