Convoy tracking for ADAS on embedded GPUs

Fickenscher, Jörg; Reinhart, Sebastian; Hannig, Frank; Teich, Jürgen; Bouzouraa, Mohamed Essayed

doi:10.1109/ivs.2017.7995839

Cited by 11 publications

(9 citation statements)

References 12 publications

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“…2 The kernel is driven via the function clEnqueueNDRangeKernel to the command queue and is ready for execution. 3 The output data is generated after the kernel is completed and the results are read back from the device to the host via function call of clEnqueueReadBuffer. 4 The data on the device and the host is synchronized over and ready for future use, which is notified by the completion of corresponding kernel events via the function clWaitForEvents.…”

Section: Accelerator Execution Overlapping (Eo)mentioning

confidence: 99%

“…In this way, the comparison of the computational capacity of each accelerator is fair and intuitive. 3 We provide a detailed procedure that contains various approaches to optimise a native parallelized application in a fine-grained manner. Therefore, this procedure applies to any OpenCL application that is developed in the early-design stage and intended to be executed in such an FPGA-GPU heterogeneous system.…”

Section: Introductionmentioning

confidence: 99%

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Performance Optimisation of Parallelized ADAS Applications in FPGA-GPU Heterogeneous Systems: A Case Study With Lane Detection

Wang

Huang

Knoll

2019

IEEE Trans. Intell. Veh.

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The explosive growth of massive data captured by various sensors on modern vehicles has impelled the deployment of Commercial Off-The-Shelf (COTS) accelerators for the research and development of Advanced Driver Assistance Systems (ADAS). Although the advent of cross-platform programming framework such as Open Computing Language (OpenCL) facilitates the programmability of ADAS applications on heterogeneous devices, the performance portability is still vulnerable and subject to different hardware implementations by the heterogeneous manufacturers. With this issue in mind, in this article we propose a detailed procedure that helps guide the performance optimisation of parallelized ADAS applications in an FPGA-GPU combined heterogeneous system. Taking two different lane detection applications as case studies, we provide one intra-accelerator and two interaccelerator optimisation methods, as well as both FPGA-specific and application-oriented optimisation strategies, to boost the program runtime performance. Experiment results on a heterogeneous platform with COTS FPGA and GPU components reveal that the optimal designs generated from the procedure can improve the runtime performance of the two applications by an average of 109.21% and 83.48% over the native parallel implementations, respectively.

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Section: Accelerator Execution Overlapping (Eo)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance Optimisation of Parallelized ADAS Applications in FPGA-GPU Heterogeneous Systems: A Case Study With Lane Detection

Wang

Huang

Knoll

2019

IEEE Trans. Intell. Veh.

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“…GPUs offer multiple parallelism levels; however, properly managing their computational resources becomes a very challenging task. Embedded systems with SoC including GPUs are used in critical domains, such as advanced driver assistance systems [1], avionics or space applications [2], [3].…”

Section: Introductionmentioning

confidence: 99%

Comparison of Parallel Implementation Strategies in GPU-Accelerated System-on-Chip Under Proton Irradiation

Badía

León

Belloch

et al. 2022

IEEE Trans. Nucl. Sci.

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Commercial Off-The-Shelf (COTS) System-on-Chip (SoC) are becoming widespread in embedded systems. Many of them include a multicore CPU and a high-end GPU. They combine high computational performance with low power consumption and flexible multilevel parallelism. This kind of device is also being considered for radiation environments where large amounts of data must be processed or compute intensive applications must be executed. In this paper we compare three different strategies to perform matrix multiplication in the GPU of a Tegra TK1 SoC. Our aim is to analyze how the different use of the resources of the GPU influences, not only the computational performance of the algorithm, but also its radiation sensitivity. Radiation experiments with protons were performed to compare the behaviour of the three strategies. Experimental results show that most of the errors force a reboot of the platform. The number of errors is directly related with how the algorithms use the internal memories of the GPU, and increases with the matrix size. It is also related with the number of transactions with the global memory, which in our experiments is not affected by the radiation. Results show that the smallest cross-section is obtained with the fastest algorithm, even if it uses the cores of the GPU more intensively.

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“…The reliability of these devices is especially important in two environments: supercomputer sites and embedded systems used in safety-critical domains. On the former, most of the TOP500 supercomputer sites 1 include high-end GPUs using state-of the-art technology and consisting of a very large number of cores, complex schedulers, large registers and caches. Due to the huge number of GPUs included in these sites, their probability of failure grows rapidly.…”

Section: Introductionmentioning

confidence: 99%

“…Due to the huge number of GPUs included in these sites, their probability of failure grows rapidly. On the latter, GPUs are one of the main components of embedded systems used in critical domains, such as advanced driver assistance systems [1], avionics or space applications [2,3]. In these domains other parameters such as the size or the energy consumption have to be taken into account.…”

Section: Introductionmentioning

confidence: 99%

Evaluating the soft error sensitivity of a GPU-based SoC for matrix multiplication

León

Badía

Belloch

et al. 2020

Microelectronics Reliability

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System-on-Chip (SoC) devices can be composed of low-power multicore processors combined with a small graphics accelerator (or GPU) which offers a trade-off between computational capacity and low-power consumption. In this work we use the LLFI-GPU fault injection tool on one of these devices to compare the sensitivity to soft errors of two different CUDA versions of matrix multiplication benchmark. Specifically, we perform fault injection campaigns on a Jetson TK1 development kit, a board equipped with a SoC including an NVIDIA "Kepler" Graphics Processing Unit (GPU). We evaluate the effect of modifying the size of the problem and also the thread-block size on the behaviour of the algorithms. Our results show that the block version of the matrix multiplication benchmark that leverages the shared memory of the GPU is not only faster than the element-wise version, but it is also much more resilient to soft errors. We also use the cuda-gdb debugger to analyze the main causes of the crashes in the code due to soft errors. Our experiments show that most of the errors are due to accesses to invalid positions of the different memories of the GPU, which causes that the block version suffers a higher percentage of this kind of errors.

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Convoy tracking for ADAS on embedded GPUs

Cited by 11 publications

References 12 publications

Performance Optimisation of Parallelized ADAS Applications in FPGA-GPU Heterogeneous Systems: A Case Study With Lane Detection

Performance Optimisation of Parallelized ADAS Applications in FPGA-GPU Heterogeneous Systems: A Case Study With Lane Detection

Comparison of Parallel Implementation Strategies in GPU-Accelerated System-on-Chip Under Proton Irradiation

Evaluating the soft error sensitivity of a GPU-based SoC for matrix multiplication

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