Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips

Ozaki, Nobuyuki; Yoshihiro, Yasuda; Saito, Yoshiki; Ikebuchi, Daisuke; Kimura, Masayuki; Amano, Hideharu; Nakamura, Hiroshi; Usami, Kimiyoshi; Namiki, Mitaro; Kondo, Masaaki

doi:10.1109/mm.2011.94

Cited by 53 publications

(20 citation statements)

References 6 publications

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“…The energy efficiency of CMA-1 has been compared with other accelerators [14][4] and it achieved the best energy efficiency in accelerators with 65nm standard CMOS process [10]. Thus, CMAGeyser can be also the energy efficient system with a CPU and an accelerator if the system size is limited.…”

Section: Discussionmentioning

confidence: 99%

“…The first prototype, CMA-1 [10] with 8 × 8 PE array was fabricated in 2.1 × 4.2mm 2 65-nm CMOS technology, and achieved 2.7-GOPS/11.2-mW sustained performance. Figure 1 shows the block diagram of CMA-1.…”

Section: Prototype Chip Cma-1mentioning

confidence: 99%

“…CMA (Cool Mega Array) [10] is a CGRA architecture especially designed focusing on energy efficiency.…”

Section: Introductionmentioning

confidence: 99%

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A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA

Mai

Ozaki

Koizumi

et al. 2015

IJNC

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Cool Mega Array (CMA) is an energy efficient reconfigurable accelerator consisting of a large PE array with combinatorial circuits and a small microcontroller. In order to enhance the energy efficiency of the total system, a co-processor design of CMA called CMA-Geyser is proposed. By partly replacing the programmable microcontroller by the host processor Geyser with a dedicated hardware controller, the setting up for the CMA and data transfer can be efficiently done.The design using 65nm CMOS process is compared with an off-loading style multicore system Cube-1. By eliminating the data memory required in Cube-1, CMA-Geyser reduced 21.3% of semiconductor area. Also, it achieved about 2.7 times performance of Cube-1 by the efficient data communication between host and the accelerator.

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Section: Discussionmentioning

confidence: 99%

Section: Prototype Chip Cma-1mentioning

confidence: 99%

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A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA

Mai

Ozaki

Koizumi

et al. 2015

IJNC

Self Cite

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“…It consists of a low-power microprocessor called Geyser [9] and coarse grained accelerators called CMACube [10] connected with the wireless inductive coupling Thru-Chip Interface (TCI). In Cube-1, a uni-directional ring network with bubble-flow control [11] is formed just by stacking chips.…”

Section: Introductionmentioning

confidence: 99%

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Nomura

Matsushita

Kadomoto

et al. 2018

IJNC

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A wireless inductive coupling ThruChip Interface (TCI) is a flexible system-in-package (SiP) technique which enables to build a powerful interconnection network between stacked chips. For easy use of TCI, we have developed intellectual properties (IPs), and proposed an interconnection network which can make the use of IPs. We also developed a real chip embedded the IP, and evaluated the performance. By stacking multiple chips with the proposed IP, an inter-chip network with link-to-link flow control by piggyback control is established. The new proposed escalator network which uses piggyback of the credit packets outperforms the ring network used in the first prototype by 28%-59% in terms of throughput. The performance overhead by the piggyback control was less than 3%-4% of that without control messages.

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“…A previously proposed CGRA, called Cool Mega Array (CMA) [4], was developed using SOTB technology , and it is called CC-SOTB (CMA Cube-SOTB). In CC-SOTB, the large PE array is consisting of combinational logic, and the data flow of the target application is mapped directly.…”

Section: Introductionmentioning

confidence: 99%