Coordinate Rotation Based Low Complexity N-D FastICA Algorithm and Architecture

Abstract

This paper proposes a low complexity n-dimensional (nD) FastICA algorithm and architecture by introducing the concept of co-ordinate rotation where n ≥ 2. The proposed algorithm can merge the two key steps of Conventional FastICA -Preprocessing and Update and is therefore capable of reducing the hardware complexity of the conventional FastICA significantly as demonstrated in this paper. Hardware implementation can further be simplified due to the recursive nature of the proposed algorithm where the same 2D hardware module can be used as the fundamental core to implement nD architecture. Together with the algorithm formulation, its functionality is also validated and hardware complexity is analyzed and compared with the conventional nD FastICA.

Coordinate Rotation-Based Low Complexity $K$ -Means Clustering Architecture

“…Since it can be realized using simple shift and add operations, it is very effective in terms of low hardware complexity [11]. Considering the rotation in the clockwise direction, the basic CORDIC expressions can be expressed as…”

“…Throughout the hardware complexity analysis, we keep a generalized view of word-length b and followed the same procedure used in [11]. Since the distance computation in KMeans Clustering using CORDIC is an iterative procedure, we consider only one single iteration because the same hardware can be reused for the next iterations as well as for successive stages of CORDIC in Vectoring Mode for dimensions higher than 2.…”

“…To provide a comparison on a uniform platform, we consider only Ripple Carry Adder (RCA) and Conventional Array Multiplier (CAM) as the means of implementing the arithmetic operations. One b−bit RCA requires b full adders (FA) (in a simplified view) [11], and b X b CAM requires b * (b − 2) FA plus b half adders (HA) and b 2 AND gates [11]. Similarly, one b-bit SQRT needs 0.125 * (b + 6)b FA and XOR gates [11].…”

“…One b−bit RCA requires b full adders (FA) (in a simplified view) [11], and b X b CAM requires b * (b − 2) FA plus b half adders (HA) and b 2 AND gates [11]. Similarly, one b-bit SQRT needs 0.125 * (b + 6)b FA and XOR gates [11]. In addition, considering one FA cell requires 24 transistors, one HA cell, and one two input XOR gate consist of 12 transistors and a two input AND gate consists of six transistors [11], we can calculate TCA = 24b, TCM = 6b(5b − 6), where TC* are the transistor counts for RCA and CAM respectively.…”

“…Therefore, an algorithm-toarchitecture holistic optimization approach is necessary for maintaining its algorithmic efficiency and making it lowcomplexity from the architectural perspective. Coordinate Rotation Digital Computer (CORDIC) based architectures exploring its different transcendental functions to compute complex arithmetic operations [11]- [12] have been used widely for computationally intensive signal processing algorithms [11]- [14]. K-Means clustering algorithm has been pre-dominantly used with fore-mentioned algorithms [11]- [14].…”